From 6635dd2ffde9bda671133b91265811fe534cd691 Mon Sep 17 00:00:00 2001 From: Eric Wong Date: Sun, 9 Nov 2025 14:53:05 +0800 Subject: [PATCH] feat: add signal for SBO in SM90 masked gemm. Co-authored-by: Zqy11 <841971412@qq.com> Co-authored-by: AniZpZ --- csrc/apis/gemm.hpp | 20 ++++++++++++---- csrc/jit_kernels/heuristics/common.hpp | 10 ++++++-- csrc/jit_kernels/impls/sm90_fp8_gemm_1d2d.hpp | 23 ++++++++++++++----- csrc/python_api.cpp | 9 +++++--- deep_gemm/include/deep_gemm/common/utils.cuh | 10 ++++++++ .../deep_gemm/impls/sm90_fp8_gemm_1d2d.cuh | 16 +++++++++++-- 6 files changed, 71 insertions(+), 17 deletions(-) diff --git a/csrc/apis/gemm.hpp b/csrc/apis/gemm.hpp index 68ac750..7db0dc8 100644 --- a/csrc/apis/gemm.hpp +++ b/csrc/apis/gemm.hpp @@ -175,14 +175,17 @@ static void m_grouped_fp8_gemm_nn_contiguous(const std::pair& a, +static std::optional> m_grouped_fp8_gemm_nt_masked(const std::pair& a, const std::pair& b, const torch::Tensor& d, const torch::Tensor& masked_m, const int& expected_m, std::optional> recipe, const std::string& compiled_dims, - const bool& disable_ue8m0_cast) { + const bool& disable_ue8m0_cast, + const int& max_block_n, + const bool& enable_overlap, + const c10::optional& signal) { // Shape must be `[G, M, K] @ [G, N, K].mT` const auto& major_a = get_major_type_ab(a.first); const auto& major_b = get_major_type_ab(b.first); @@ -202,6 +205,12 @@ static void m_grouped_fp8_gemm_nt_masked(const std::pairget_arch_major(); + std::optional> result = std::nullopt; if (arch_major == 9 and sfa.scalar_type() == torch::kFloat) { - sm90_m_grouped_fp8_gemm_masked_1d2d(a.first, sfa, b.first, sfb, d, masked_m, - num_groups, m, n, k, expected_m, major_a, major_b, compiled_dims); + result = sm90_m_grouped_fp8_gemm_masked_1d2d(a.first, sfa, b.first, sfb, d, masked_m, + num_groups, m, n, k, expected_m, major_a, major_b, compiled_dims, + max_block_n, enable_overlap, signal); } else if (arch_major == 10 and sfa.scalar_type() == torch::kInt) { sm100_m_grouped_fp8_gemm_masked_1d1d(a.first, sfa, b.first, sfb, d, masked_m, num_groups, m, n, k, expected_m, major_a, major_b, compiled_dims); @@ -225,6 +236,7 @@ static void m_grouped_fp8_gemm_nt_masked(const std::pair& a, diff --git a/csrc/jit_kernels/heuristics/common.hpp b/csrc/jit_kernels/heuristics/common.hpp index 455223b..969056e 100644 --- a/csrc/jit_kernels/heuristics/common.hpp +++ b/csrc/jit_kernels/heuristics/common.hpp @@ -63,6 +63,7 @@ struct GemmConfig { cute::UMMA::Major major_b; bool with_accumulation; int block_m, block_n, block_k; + int signal_threshold; int num_stages, num_last_stages; // Templated device configs @@ -73,6 +74,8 @@ struct GemmConfig { MulticastConfig multicast_config; SharedMemoryConfig smem_config; ThreadConfig thread_config; + + bool enable_overlap; }; static bool is_multicast_legal(const int& shape_dim, const int& block_dim, @@ -151,7 +154,8 @@ static GemmConfig get_best_config(const GemmType& gemm_type, const KernelType& k const int& m, const int& n, const int& k, const int& num_groups, const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b, const at::ScalarType& ab_dtype, const at::ScalarType& cd_dtype, - const bool& with_accumulation, const int& num_sms) { + const bool& with_accumulation, const int& num_sms, + const int& max_block_n = 256, const bool& enable_overlap = false) { DG_HOST_ASSERT(ab_dtype == torch::kFloat8_e4m3fn or ab_dtype == torch::kBFloat16); DG_HOST_ASSERT(cd_dtype == torch::kBFloat16 or cd_dtype == torch::kFloat); @@ -271,6 +275,7 @@ static GemmConfig get_best_config(const GemmType& gemm_type, const KernelType& k .block_m = best_block_m, .block_n = best_block_n, .block_k = block_k, + .signal_threshold = ceil_div(n, best_block_n), .num_stages = best_num_stages, .num_last_stages = ceil_div(k, block_k) % best_num_stages, .num_sms = num_min_sms, @@ -278,7 +283,8 @@ static GemmConfig get_best_config(const GemmType& gemm_type, const KernelType& k .multicast_config = best_multicast_config, // ReSharper disable once CppLocalVariableMightNotBeInitialized .smem_config = best_smem_config, - .thread_config = ArchSpec::get_thread_config(kernel_type, best_block_m, best_block_n) + .thread_config = ArchSpec::get_thread_config(kernel_type, best_block_m, best_block_n), + .enable_overlap = enable_overlap }; // Only SM100 BF16 kernels support tensor core control diff --git a/csrc/jit_kernels/impls/sm90_fp8_gemm_1d2d.hpp b/csrc/jit_kernels/impls/sm90_fp8_gemm_1d2d.hpp index ced8d17..b348a19 100644 --- a/csrc/jit_kernels/impls/sm90_fp8_gemm_1d2d.hpp +++ b/csrc/jit_kernels/impls/sm90_fp8_gemm_1d2d.hpp @@ -22,7 +22,7 @@ public: GemmConfig gemm_config; LaunchArgs launch_args; - void *sfb, *grouped_layout; + void *sfb, *grouped_layout, *signal; CUtensorMap tensor_map_a; CUtensorMap tensor_map_b; CUtensorMap tensor_map_d; @@ -44,7 +44,8 @@ static void __instantiate_kernel() {{ {}, {}, {}, {}, {}, {}, - {}, {}, {} + {}, {}, {}, + {} >); }}; )", @@ -57,13 +58,14 @@ static void __instantiate_kernel() {{ args.gemm_config.thread_config.num_tma_threads, args.gemm_config.thread_config.num_math_threads, args.gemm_config.multicast_config.num_multicast, args.gemm_config.multicast_config.is_multicast_on_a, args.gemm_config.num_sms, to_string(args.gemm_config.gemm_type), - get_default_epilogue_type(args.epilogue_type)); + get_default_epilogue_type(args.epilogue_type), + args.gemm_config.enable_overlap); } static void launch_impl(const KernelHandle& kernel, const LaunchConfigHandle& config, Args args) { // TODO: optimize `args` copy DG_CUDA_UNIFIED_CHECK(launch_kernel(kernel, config, - args.sfb, args.grouped_layout, + args.sfb, args.grouped_layout, args.signal, args.m, args.n, args.k, args.tensor_map_a, args.tensor_map_b, args.tensor_map_d, args.tensor_map_sfa)); @@ -121,6 +123,7 @@ static void sm90_fp8_gemm_1d2d(const torch::Tensor& a, const torch::Tensor& sfa, config.multicast_config.num_multicast), .sfb = sfb.data_ptr(), .grouped_layout = nullptr, + .signal = nullptr, .tensor_map_a = tensor_map_a, .tensor_map_b = tensor_map_b, .tensor_map_d = tensor_map_d, @@ -181,6 +184,7 @@ static void sm90_m_grouped_fp8_gemm_contiguous_1d2d(const torch::Tensor& a, cons config.multicast_config.num_multicast), .sfb = sfb.data_ptr(), .grouped_layout = m_indices.data_ptr(), + .signal = nullptr, .tensor_map_a = tensor_map_a, .tensor_map_b = tensor_map_b, .tensor_map_d = tensor_map_d, @@ -198,7 +202,10 @@ static void sm90_m_grouped_fp8_gemm_masked_1d2d(const torch::Tensor& a, const to const int& num_groups, const int& m, const int& n, const int& k, const int& expected_m, const cute::UMMA::Major& major_a, const cute::UMMA::Major& major_b, - const std::string& compiled_dims) { + const std::string& compiled_dims, + const int& max_block_n, + const bool& enable_overlap, + const c10::optional& signal) { const auto& aligned_k = align(k, 128); DG_HOST_ASSERT(d.scalar_type() == torch::kBFloat16); DG_HOST_ASSERT(major_a == cute::UMMA::Major::K and major_b == cute::UMMA::Major::K); @@ -207,7 +214,7 @@ static void sm90_m_grouped_fp8_gemm_masked_1d2d(const torch::Tensor& a, const to GemmType::MGroupedMasked, KernelType::Kernel1D2D, expected_m, n, k, num_groups, major_a, major_b, torch::kFloat8_e4m3fn, d.scalar_type(), false, - device_runtime->get_num_sms()); + device_runtime->get_num_sms(), max_block_n, enable_overlap); // Requires no TMA splits DG_HOST_ASSERT(config.smem_config.swizzle_a_mode == config.block_k); @@ -242,6 +249,7 @@ static void sm90_m_grouped_fp8_gemm_masked_1d2d(const torch::Tensor& a, const to config.multicast_config.num_multicast), .sfb = sfb.data_ptr(), .grouped_layout = masked_m.data_ptr(), + .signal = enable_overlap ? signal.value().data_ptr() : nullptr, .tensor_map_a = tensor_map_a, .tensor_map_b = tensor_map_b, .tensor_map_d = tensor_map_d, @@ -250,6 +258,9 @@ static void sm90_m_grouped_fp8_gemm_masked_1d2d(const torch::Tensor& a, const to const auto& code = SM90FP8Gemm1D2DRuntime::generate(args); const auto& runtime = compiler->build("sm90_fp8_m_grouped_gemm_masked_1d2d", code); MAYBE_LAUNCH(SM90FP8Gemm1D2DRuntime::launch(runtime, args)); + return enable_overlap ? + std::optional(std::make_pair(config.block_m, config.signal_threshold)) : + std::nullopt; } } // namespace deep_gemm diff --git a/csrc/python_api.cpp b/csrc/python_api.cpp index 2b2b518..e75eeac 100644 --- a/csrc/python_api.cpp +++ b/csrc/python_api.cpp @@ -342,17 +342,20 @@ TORCH_LIBRARY(deep_gemm, m) { deep_gemm_wrappers::m_grouped_fp8_gemm_nn_contiguous_wrapper(a_val, a_scale, b_val, b_scale, d, m_indices, recipe, compiled_dims, disable_ue8m0_cast); }); - m.def(R"(m_grouped_fp8_gemm_nt_masked(Any a, Any b, Tensor d, Tensor masked_m, int expected_m, int[]? recipe=None, str compiled_dims="nk", bool disable_ue8m0_cast=False) -> ())"); + m.def(R"(m_grouped_fp8_gemm_nt_masked(Any a, Any b, Tensor d, Tensor masked_m, int expected_m, int[]? recipe=None, str compiled_dims="nk", bool disable_ue8m0_cast=False, int max_block_n=256, bool enable_overlap=False, Tensor? signal=None) -> (int?, int?))"); m.impl("m_grouped_fp8_gemm_nt_masked", torch::kCUDA, [](const c10::IValue& a_input, const c10::IValue& b_input, const torch::Tensor& d, const torch::Tensor& masked_m, int64_t expected_m, const c10::optional& recipe, const std::string& compiled_dims, - bool disable_ue8m0_cast) { + bool disable_ue8m0_cast, + int64_t max_block_n, + bool enable_overlap, + const c10::optional& signal) { auto [a_val, a_scale] = parse_tensor_or_tuple(a_input); auto [b_val, b_scale] = parse_tensor_or_tuple(b_input); - deep_gemm_wrappers::m_grouped_fp8_gemm_nt_masked_wrapper(a_val, a_scale, b_val, b_scale, d, masked_m, expected_m, recipe, compiled_dims, disable_ue8m0_cast); + return deep_gemm_wrappers::m_grouped_fp8_gemm_nt_masked_wrapper(a_val, a_scale, b_val, b_scale, d, masked_m, expected_m, recipe, compiled_dims, disable_ue8m0_cast, max_block_n, enable_overlap, signal); }); m.def(R"(k_grouped_fp8_gemm_nt_contiguous(Any a, Any b, Tensor d, int[] ks, Tensor ks_tensor, Tensor? c=None, int[] recipe=[1, 1, 128], str compiled_dims="mn") -> ())"); diff --git a/deep_gemm/include/deep_gemm/common/utils.cuh b/deep_gemm/include/deep_gemm/common/utils.cuh index 0b7ff11..d590e61 100644 --- a/deep_gemm/include/deep_gemm/common/utils.cuh +++ b/deep_gemm/include/deep_gemm/common/utils.cuh @@ -158,6 +158,16 @@ __device__ __forceinline__ void prefetch_l1(void *ptr) { asm volatile("prefetch.global.L1 [%0];" :: "l"(ptr)); } +__device__ __forceinline__ void store_wait() { + asm volatile("cp.async.bulk.wait_group 0;\n" ::: "memory"); +} + +__device__ __forceinline__ int atomic_add_release_global(int* addr, int value) { + int ret; + asm volatile ("atom.add.release.gpu.global.s32 %0, [%1], %2;" : "=r"(ret) : "l"(addr), "r"(value)); + return ret; +} + template struct Vectorized { static auto zeros() { diff --git a/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d2d.cuh b/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d2d.cuh index 5a92d7d..ea4b505 100644 --- a/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d2d.cuh +++ b/deep_gemm/include/deep_gemm/impls/sm90_fp8_gemm_1d2d.cuh @@ -38,9 +38,9 @@ template + typename epilogue_type_t, bool kEnableOverlap> __global__ __launch_bounds__(kNumTMAThreads + kNumMathThreads, 1) void -sm90_fp8_gemm_1d2d_impl(float* sfb, int* grouped_layout, +sm90_fp8_gemm_1d2d_impl(float* sfb, int* grouped_layout, int *signal, uint32_t shape_m, uint32_t shape_n, uint32_t shape_k, const __grid_constant__ cute::TmaDescriptor tensor_map_a, const __grid_constant__ cute::TmaDescriptor tensor_map_b, @@ -395,6 +395,18 @@ sm90_fp8_gemm_1d2d_impl(float* sfb, int* grouped_layout, cute::tma_store_arrive(); } __syncwarp(); + + if constexpr (kEnableOverlap) { + if (threadIdx.x < BLOCK_N / TMA_D_BLOCK_N) { + store_wait(); + } + + cutlass::arch::NamedBarrier(kNumMathThreads).sync(); + + if (threadIdx.x == 0) { + atomic_add_release_global(signal + scheduler.current_group_idx * ceil_div(shape_m, BLOCK_M) + m_block_idx, 1); + } + } } } #else