62750a2b75
* v3.8 update x * fix blackwell gg * doc change * doc change * doc change --------- Co-authored-by: yuzhai <yuzhai@nvidia.com> Co-authored-by: Haicheng Wu <haichengw@nvidia.com> Co-authored-by: Haicheng Wu <57973641+hwu36@users.noreply.github.com>
3445 lines
126 KiB
C++
3445 lines
126 KiB
C++
/***************************************************************************************************
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* Copyright (c) 2025 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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#pragma once
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#include <cute/arch/config.hpp>
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#include <cute/arch/mma.hpp>
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#include <cute/numeric/numeric_types.hpp> // cute::float_e4m3_t, etc
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#include <cute/arch/mma_sm120.hpp>
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#include <cutlass/detail/dependent_false.hpp>
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namespace cute {
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namespace SM120::SPARSE {
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////////////////////////////////////////////////////////////////////////////////////////////////////
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template <class a_type, class b_type, class c_type>
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struct SM120_SPARSE_16x8x64_TN
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{
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static_assert(cutlass::detail::dependent_false<a_type>, "No MMA matches SM120_SPARSE_16x8x64_TN for given data types.");
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E2M1 x E2M1
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e2m1_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m1.e2m1.f32 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"%16, 0x0;\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E2M1 x E3M2
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e3m2_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m1.e3m2.f32 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"%16, 0x0;\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E2M1 x E2M3
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e2m3_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m1.e2m3.f32 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"%16, 0x0;\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E2M1 x E4M3
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e4m3_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m1.e4m3.f32 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"%16, 0x0;\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E2M1 x E5M2
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e5m2_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m1.e5m2.f32 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"%16, 0x0;\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E3M2 x E2M1
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e2m1_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e3m2.e2m1.f32 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"%16, 0x0;\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x64 TN with FP32 ACC and inputs E3M2 x E3M2
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template <>
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struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e3m2_t, float>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e)
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{
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#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e3m2.e3m2.f32 "
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"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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}
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};
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|
|
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////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
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// MMA 16x8x64 TN with FP32 ACC and inputs E3M2 x E2M3
|
|
template <>
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|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e2m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
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using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
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|
fma(float & d0, float & d1, float & d2, float & d3,
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|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
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|
asm volatile(
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|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e3m2.e2m3.f32 "
|
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"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e));
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#else
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|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
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#endif
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|
}
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|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E3M2 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e4m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
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|
using CRegisters = float[4];
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|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
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|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e3m2.e4m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E3M2 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e5m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e3m2.e5m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E2M3 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e2m1_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m3.e2m1.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E2M3 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e3m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m3.e3m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E2M3 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e2m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m3.e2m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E2M3 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e4m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m3.e4m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E2M3 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e5m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e2m3.e5m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E4M3 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e2m1_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e4m3.e2m1.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E4M3 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e3m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e4m3.e3m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E4M3 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e2m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e4m3.e2m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E4M3 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e4m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e4m3.e4m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E4M3 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e5m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e4m3.e5m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E5M2 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e2m1_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e5m2.e2m1.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E5M2 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e3m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e5m2.e3m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E5M2 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e2m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e5m2.e2m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E5M2 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e4m3_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e5m2.e4m3.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP32 ACC and inputs E5M2 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e5m2_t, float>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f32.e5m2.e5m2.f32 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"%16, 0x0;\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M1 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e2m1_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m1.e2m1.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M1 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e3m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m1.e3m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M1 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e2m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m1.e2m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M1 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e4m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m1.e4m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M1 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m1_t, float_e5m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m1.e5m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E3M2 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e2m1_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e3m2.e2m1.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E3M2 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e3m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e3m2.e3m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E3M2 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e2m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e3m2.e2m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E3M2 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e4m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e3m2.e4m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E3M2 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e3m2_t, float_e5m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e3m2.e5m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M3 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e2m1_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m3.e2m1.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M3 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e3m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m3.e3m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M3 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e2m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m3.e2m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M3 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e4m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m3.e4m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E2M3 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e2m3_t, float_e5m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e2m3.e5m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E4M3 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e2m1_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e4m3.e2m1.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E4M3 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e3m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e4m3.e3m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E4M3 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e2m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e4m3.e2m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E4M3 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e4m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e4m3.e4m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E4M3 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e4m3_t, float_e5m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e4m3.e5m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E5M2 x E2M1
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e2m1_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e5m2.e2m1.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E5M2 x E3M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e3m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e5m2.e3m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E5M2 x E2M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e2m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e5m2.e2m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E5M2 x E4M3
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e4m3_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e5m2.e4m3.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA 16x8x64 TN with FP16 ACC and inputs E5M2 x E5M2
|
|
template <>
|
|
struct SM120_SPARSE_16x8x64_TN<float_e5m2_t, float_e5m2_t, half_t>
|
|
{
|
|
using DRegisters = uint32_t[2];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = uint32_t[2];
|
|
using ERegisters = uint32_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(uint32_t & d0, uint32_t & d1,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
uint32_t const& c0, uint32_t const& c1,
|
|
uint32_t const& e)
|
|
{
|
|
#if defined(CUTE_ARCH_F8F6F4_MMA_ENABLED)
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::f8f6f4.sp::ordered_metadata.m16n8k64.row.col.f16.e5m2.e5m2.f16 "
|
|
"{%0, %1},"
|
|
"{%2, %3, %4, %5},"
|
|
"{%6, %7, %8, %9},"
|
|
"{%10, %11},"
|
|
"%12, 0x0;\n"
|
|
: "=r"(d0), "=r"(d1)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"r"(c0), "r"(c1),
|
|
"r"(e));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN without CUTE_ARCH_F8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
} // end namespace SM120::SPARSE
|
|
|
|
namespace SM120::BLOCKSCALED::SPARSE {
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
template <class a_type, class b_type, class c_type, class sf_type, int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS
|
|
{
|
|
static_assert(cutlass::detail::dependent_false<a_type>, "No MMA matches SM120_SPARSE_16x8x64_TN_VS for given data types.");
|
|
};
|
|
|
|
template <class a_type, class b_type, class c_type, class sf_type, int VS>
|
|
struct SM120_SPARSE_16x8x128_TN_VS
|
|
{
|
|
static_assert(cutlass::detail::dependent_false<a_type>, "No MMA matches SM120_SPARSE_16x8x128_TN_VS for given data types.");
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M1 x E2M1, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m1_t, float_e2m1_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m1.e2m1.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M1 x E3M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m1_t, float_e3m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m1.e3m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M1 x E2M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m1_t, float_e2m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m1.e2m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M1 x E4M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m1_t, float_e4m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m1.e4m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M1 x E5M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m1_t, float_e5m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m1.e5m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E3M2 x E2M1, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e3m2_t, float_e2m1_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e3m2.e2m1.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E3M2 x E3M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e3m2_t, float_e3m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e3m2.e3m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E3M2 x E2M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e3m2_t, float_e2m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e3m2.e2m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E3M2 x E4M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e3m2_t, float_e4m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e3m2.e4m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E3M2 x E5M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e3m2_t, float_e5m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e3m2.e5m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M3 x E2M1, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m3_t, float_e2m1_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m3.e2m1.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M3 x E3M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m3_t, float_e3m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m3.e3m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M3 x E2M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m3_t, float_e2m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m3.e2m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M3 x E4M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m3_t, float_e4m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m3.e4m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E2M3 x E5M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e2m3_t, float_e5m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e2m3.e5m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E4M3 x E2M1, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e4m3_t, float_e2m1_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e4m3.e2m1.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E4M3 x E3M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e4m3_t, float_e3m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e4m3.e3m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E4M3 x E2M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e4m3_t, float_e2m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e4m3.e2m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E4M3 x E4M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e4m3_t, float_e4m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e4m3.e4m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E4M3 x E5M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e4m3_t, float_e5m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e4m3.e5m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E5M2 x E2M1, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e5m2_t, float_e2m1_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e5m2.e2m1.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E5M2 x E3M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e5m2_t, float_e3m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e5m2.e3m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E5M2 x E2M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e5m2_t, float_e2m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e5m2.e2m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E5M2 x E4M3, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e5m2_t, float_e4m3_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e5m2.e4m3.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x64 TN with FP32 ACC and inputs E5M2 x E5M2, SF UE8M0
|
|
template <int VS>
|
|
struct SM120_SPARSE_16x8x64_TN_VS<float_e5m2_t, float_e5m2_t, float, float_ue8m0_t, VS>
|
|
{
|
|
using DRegisters = float[4];
|
|
using ARegisters = uint32_t[4];
|
|
using BRegisters = uint32_t[4];
|
|
using CRegisters = float[4];
|
|
using ERegisters = uint32_t[1];
|
|
using SFARegisters = uint8_t[1];
|
|
using SFBRegisters = uint8_t[1];
|
|
|
|
CUTE_HOST_DEVICE static void
|
|
fma(float & d0, float & d1, float & d2, float & d3,
|
|
uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
|
|
uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
|
|
float const& c0, float const& c1, float const& c2, float const& c3,
|
|
uint32_t const& e, uint8_t const& sfa, uint8_t const& sfb)
|
|
{
|
|
#if defined(CUTE_ARCH_MXF8F6F4_MMA_ENABLED)
|
|
static constexpr uint16_t tidA = 0;
|
|
static constexpr uint16_t bidA = 0;
|
|
static constexpr uint16_t tidB = 0;
|
|
static constexpr uint16_t bidB = 0;
|
|
|
|
CUTE_STATIC_ASSERT(VS == 64, "Scaling factor vector size has to be 64 for MXF8F6F4 MMA.");
|
|
|
|
asm volatile(
|
|
"mma.sync.aligned.kind::mxf8f6f4.sp::ordered_metadata.block_scale.scale_vec::1X.m16n8k64.row.col.f32.e5m2.e5m2.f32.ue8m0 "
|
|
"{%0, %1, %2, %3},"
|
|
"{%4, %5, %6, %7},"
|
|
"{%8, %9, %10, %11},"
|
|
"{%12, %13, %14, %15},"
|
|
"{%16}, 0x0,"
|
|
"{%17},"
|
|
"{%18, %19},"
|
|
"{%20},"
|
|
"{%21, %22};\n"
|
|
: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
|
|
: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
|
|
"r"(b0), "r"(b1), "r"(b2), "r"(b3),
|
|
"f"(c0), "f"(c1), "f"(c2), "f"(c3),
|
|
"r"(e),
|
|
"r"((uint32_t)sfa), "h"(bidA), "h"(tidA),
|
|
"r"((uint32_t)sfb), "h"(bidB), "h"(tidB));
|
|
#else
|
|
CUTE_INVALID_CONTROL_PATH("Attempting to use SM120_SPARSE_16x8x64_TN_VS without CUTE_ARCH_MXF8F6F4_MMA_ENABLED");
|
|
#endif
|
|
}
|
|
};
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MMA SPARSE BLOCKSCALED 16x8x128 TN E2M1 x E2M1 with SF UE8M0
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template <int VS>
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struct SM120_SPARSE_16x8x128_TN_VS<float_e2m1_t, float_e2m1_t, float, float_ue8m0_t, VS>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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static constexpr int SFBits = (VS == 64) ? 16 : 32;
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using RegTypeSF = uint_bit_t<SFBits>;
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using SFARegisters = RegTypeSF[1];
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using SFBRegisters = RegTypeSF[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e, RegTypeSF const& sfa, RegTypeSF const& sfb)
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{
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static constexpr uint16_t tidA = 0;
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static constexpr uint16_t bidA = 0;
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static constexpr uint16_t tidB = 0;
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static constexpr uint16_t bidB = 0;
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CUTE_STATIC_ASSERT(VS == 64 || VS == 32, "Scaling factor vector size has to be 64 or 32 for MXF4NVF4.");
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#if defined(CUTE_ARCH_MXF4NVF4_2X_UE8M0_MMA_ENABLED)
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asm volatile(
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"mma.sync.aligned.kind::mxf4nvf4.sp::ordered_metadata.block_scale.scale_vec::2X.m16n8k128.row.col.f32.e2m1.e2m1.f32.ue8m0 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"{%16}, 0x0,"
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"{%17}, {%18, %19},"
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"{%20}, {%21, %22};\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e),
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"r"(uint32_t(sfa)), "h"(bidA), "h"(tidA),
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"r"(uint32_t(sfb)), "h"(bidB), "h"(tidB));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120::SPARSE::SM120_SPARSE_16x8x128_TN_VS without CUTE_ARCH_MXF4NVF4_2X_UE8M0_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA SPARSE BLOCKSCALED 16x8x128 TN E2M1 x E2M1 with SF E4M3
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template <int VS>
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struct SM120_SPARSE_16x8x128_TN_VS<float_e2m1_t, float_e2m1_t, float, float_ue4m3_t, VS>
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{
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using DRegisters = float[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[4];
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using CRegisters = float[4];
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using ERegisters = uint32_t[1];
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static constexpr int SFBits = (VS == 64) ? 16 : 32;
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using RegTypeSF = uint_bit_t<SFBits>;
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using SFARegisters = RegTypeSF[1];
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using SFBRegisters = RegTypeSF[1];
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CUTE_HOST_DEVICE static void
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fma(float & d0, float & d1, float & d2, float & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1, uint32_t const& b2, uint32_t const& b3,
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float const& c0, float const& c1, float const& c2, float const& c3,
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uint32_t const& e, RegTypeSF const& sfa, RegTypeSF const& sfb)
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{
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#if defined(CUTE_ARCH_MXF4NVF4_4X_UE4M3_MMA_ENABLED)
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static constexpr uint16_t tidA = 0;
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static constexpr uint16_t bidA = 0;
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static constexpr uint16_t tidB = 0;
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static constexpr uint16_t bidB = 0;
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CUTE_STATIC_ASSERT(VS == 32, "Scaling factor vector size has to be 32 for NVF4 with e2m1 and scale factor e4m3.");
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asm volatile(
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"mma.sync.aligned.kind::mxf4nvf4.sp::ordered_metadata.block_scale.scale_vec::4X.m16n8k128.row.col.f32.e2m1.e2m1.f32.ue4m3 "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9, %10, %11},"
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"{%12, %13, %14, %15},"
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"{%16}, 0x0,"
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"{%17}, {%18, %19},"
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"{%20}, {%21, %22};\n"
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: "=f"(d0), "=f"(d1), "=f"(d2), "=f"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1), "r"(b2), "r"(b3),
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"f"(c0), "f"(c1), "f"(c2), "f"(c3),
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"r"(e),
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"r"(uint32_t(sfa)), "h"(bidA), "h"(tidA),
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"r"(uint32_t(sfb)), "h"(bidB), "h"(tidB));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM120::SPARSE::SM120_SPARSE_16x8x128_TN_VS without CUTE_ARCH_MXF4NVF4_4X_UE4M3_MMA_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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} // end namespace SM120::BLOCKSCALED::SPARSE
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////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////
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template <
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class ElementA,
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class ElementB,
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class ElementC
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>
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CUTE_HOST_DEVICE constexpr
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auto
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rr_sparse_op_selector_sm120()
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{
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// Get MMA SPARSE OP
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return SM120::SPARSE::SM120_SPARSE_16x8x64_TN<ElementA, ElementB, ElementC>{};
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}
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template <
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class ElementA,
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class ElementB,
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class ElementC,
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class ElementSF,
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int SFVecSize,
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bool UseF8F6F4
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>
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CUTE_HOST_DEVICE constexpr
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auto
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rr_blockscaled_sparse_op_selector_sm120()
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|
{
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if constexpr (UseF8F6F4) {
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return SM120::BLOCKSCALED::SPARSE::SM120_SPARSE_16x8x64_TN_VS<ElementA, ElementB, ElementC, ElementSF, SFVecSize>{};
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}
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else {
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return SM120::BLOCKSCALED::SPARSE::SM120_SPARSE_16x8x128_TN_VS<ElementA, ElementB, ElementC, ElementSF, SFVecSize>{};
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}
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}
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} // namespace cute
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