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22 Commits
Author SHA1 Message Date
Stepan Tezyunichev 86ce09aed1 2.9 fixes for nvrtc (#480) 
* Use platform::is_same instead of std::is_same

* Don't hide cuComplex include from nvrtc

* Typo fixed

* Remove comment rename
 2022-04-29 09:06:52 -04:00
Stepan Tezyunichev 71def2f084 Use platform:: instead of std::abs and std::conditional (#452) 
* Fixed template struct/class mismatch

* Use platform implementation instead of std::abs and std::conditional during nvrtc compilation

* Use platform implementation instead of std::abs and std::conditional during nvrtc compilation

* Revert absolute_value() usage
 2022-04-25 14:40:22 -04:00
Andrew Kerr 12f4108ac2 CUTLASS 2.9 (#468) 2022-04-23 15:02:38 -04:00
Andrew Kerr 8a951b2940 Enable convolution with fused epilogue for Volta Tensor Cores (#402) 
* Enabled convolution with epilogue fusion for Volta Tensor Cores.

* Compilation fixes

* Disabled testing Volta on Ampere architectures.
 2022-01-30 23:24:50 -05:00
Manish Gupta 808c25337a CUTLASS 2.8 (#363) 
CUTLASS 2.8
 2021-11-19 13:26:35 -08:00
Manish Gupta 2e07c4cc2f CUTLASS 2.7 (#318) 
CUTLASS 2.7

Mainloop fusion for GEMM: summation over A or B
Strided DGRAD (optimized iterators)
Half-precision GELU_taylor activation functions
Use these when accumulation and epilogue compute types are all cutlass::half_t
Tuning and bug fixes to fused GEMM + GEMM example
Support for smaller than 128b aligned Convolutions: see examples
Caching of results to accelerate Convolution unit tests
Can be enabled or disabled by running cmake .. -DCUTLASS_TEST_ENABLE_CACHED_RESULTS=OFF
Corrections and bug fixes reported by the CUTLASS community
Thank you for filing these issues!

authored-by: Haicheng Wu haichengw@nvidia.com, Manish Gupta manigupta@nvidia.com, Dustyn Blasig dblasig@nvidia.com, Andrew Kerr akerr@nvidia.com
 2021-09-20 11:02:22 -07:00
Haicheng Wu 59e2aa505a refine the implementation 2021-09-08 13:14:08 +00:00
Haicheng Wu 4e8af93da1 Merge remote-tracking branch 'origin/master' into small_alignment 2021-09-07 20:39:38 +00:00
Manish GuptaandHaicheng Wu <haichengw@nvidia.com>, Andrew Kerr <akerr@nvidia.com> 6c2f8f2fb8 CUTLASS 2.6.1 - functional and performance enhancements to strided DGRAD, fixes, and tuning 
* cutlass 2.6 update

* remove debug prints

* cutlass 2.6.1 (minor update)

* Updated CHANGELOG.

* Minor edit to readme to indicate patch version.

* Minor edit to readme.

Co-authored-by:  Haicheng Wu <haichengw@nvidia.com>, Andrew Kerr <akerr@nvidia.com>
 2021-09-03 10:26:15 -07:00
Haicheng Wu 598e35401c Merge remote-tracking branch 'origin/master' into small_alignment 2021-08-16 07:49:08 -07:00
Manish Gupta 1ac4559d12 Cutlass 2.6 Update 1 (#301) 
* cutlass 2.6 update

* remove debug prints
 2021-07-27 17:58:30 -07:00
Manish Gupta e5d51840e8 CUTLASS 2.6 (#298) 
CUTLASS 2.6
 2021-07-23 00:40:53 -04:00
Haicheng Wu 5fc142296f Merge pull request #237 from Peter9606/issue_236_typo 
Typo fix issue#236
 2021-05-08 07:51:19 -04:00
mengchi.hmc f4b0a33633 add unit test for non int4 load 2021-04-23 14:33:46 +08:00
mengchi.hmc bb35a3ba6f support setting load granularity for conv2d fprop 2021-04-22 15:20:57 +08:00
mengchi.hmc 7ec3a87f22 support unalignment input for conv2d fprop stage=2 Fix for issue #242 2021-04-21 14:40:05 +08:00
Peter Han 7320aee17d Typo fix issue#236 
Signed-off-by: Peter Han <fujun.han@iluvatar.ai>
 2021-04-15 15:08:35 +08:00
Manikandan Ananth 4839b6cb61 add 2stage fprop 3d into default file 2021-04-07 13:29:32 -07:00
Manikandan Ananth 75a4737cfe Fix for public issue #211 
- Add a slice-K tile size to the profiler
- fix num warps calculations in implicit gemm header
 2021-04-01 14:42:00 -07:00
Peter Han 92393b2676 Bugfix: memsetAsync uses wrong default stream 
Signed-off-by: Peter Han <fujun.han@iluvatar.ai>
 2021-03-23 21:11:42 +08:00
Andrew Kerr 0e13748649 CUTLASS 2.5 2021-02-26 09:58:26 -05:00
Manish GuptaandManish Gupta <manigupta@nvidia.com>, Haicheng Wu <haichengw@nvidia.com>, Dustyn Blasig <dblasig@nvidia.com>, Andrew Kerr <akerr@nvidia.com> 6615010cd0 CUTLASS 2.4 (Implicit GEMM convolution) (#147) 
CUTLASS 2.4 (Implicit GEMM Convolution)

Co-authored-by: Manish Gupta <manigupta@nvidia.com>, Haicheng Wu <haichengw@nvidia.com>, Dustyn Blasig <dblasig@nvidia.com>, Andrew Kerr <akerr@nvidia.com>
 2020-11-19 21:25:25 -08:00