CUTLASS 3.3.0 (#1167)

* Release 3.3.0

Adds support for mixed precision GEMMs On Hopper and Ampere
Adds support for < 16B aligned GEMMs on Hopper
Enhancements to EVT
Enhancements to Python interface
Enhancements to Sub-byte type handling in CuTe
Several other bug-fixes and performance improvements.

* minor doc update

include/cutlass/arch/arch.h

@@ -41,7 +41,7 @@
 namespace cutlass {
 namespace arch {
 
-#if defined(__NVCC__) || (defined(__clang__) && defined(__CUDA__))
+#if defined(__NVCC__) || defined(__CUDACC_RTC__) || (defined(__clang__) && defined(__CUDA__))
 
 /// Computes laneId within a warp
 CUTLASS_DEVICE

include/cutlass/arch/barrier.h

@@ -484,6 +484,22 @@ void fence_view_async_shared() {
 #endif
 }
 
+// Arrive on completion of in-flight cp.async operations issued by the calling thread 
+CUTLASS_DEVICE
+void cpasync_barrier_arrive(uint64_t const* smem_ptr) {
+#if CUDA_BARRIER_ENABLED
+  uint32_t smem_addr = cute::cast_smem_ptr_to_uint(smem_ptr);
+  asm volatile(
+    "{\n\t"
+    "cp.async.mbarrier.arrive.shared.b64 [%0];\n\t"
+    "}"
+    :
+    : "r"(smem_addr));
+#elif defined(__CUDA_ARCH__)
+  asm volatile ("brkpt;\n" ::);
+#endif
+}
+
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////

include/cutlass/arch/mma.h

@@ -92,6 +92,7 @@ struct UseStagedAccumulation {
   static bool const value = platform::is_same<Operator, OpMultiplyAddFastF32>::value ||
                             platform::is_same<Operator, OpMultiplyAddComplexFastF32>::value;
 };
+
 /////////////////////////////////////////////////////////////////////////////////////////////////
 
 /// Tag indicating the complex multiply-add operation
@@ -128,7 +129,7 @@ struct OpClassWmmaTensorOp {};
 
 /////////////////////////////////////////////////////////////////////////////////////////////////
 
-/// Tag classifing operators as Tensor Core with structure sparse operations.
+/// Tag classifying operators as Tensor Core with structure sparse operations.
 struct OpClassSparseTensorOp {};
 
 /////////////////////////////////////////////////////////////////////////////////////////////////

include/cutlass/arch/reg_reconfig.h

@@ -55,7 +55,6 @@ void warpgroup_reg_alloc(){
   asm volatile( "setmaxnreg.inc.sync.aligned.u32 %0;\n" : : "n"(RegCount) );
 #endif
 }
-
 template<uint32_t RegCount>
 CUTLASS_DEVICE
 void warpgroup_reg_dealloc(){