CUTLASS 2.2 (#96)
Adds support for NVIDIA Ampere Architecture features. CUDA 11 Toolkit recommended.
This commit is contained in:
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# Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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# Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification, are permitted
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# provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -758,6 +758,65 @@ TEST(SM75_Epilogue_threadblock_epilogue, s8_tensor_op_128x128_64x64x16) {
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EXPECT_TRUE(passed);
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}
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TEST(SM75_Epilogue_threadblock_epilogue, s8_tensor_op_64x128_64x64x16) {
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//
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// Define the warp-level matrix multiply
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//
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using ElementOutput = int8_t;
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using ElementAccumulator = int;
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using ElementCompute = float;
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int const kElementsPerAccess = 128 / cutlass::sizeof_bits<ElementOutput>::value;
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int const kPartitionsK = 1;
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using Shape = cutlass::gemm::GemmShape<128, 128, 16>;
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using WarpShape = cutlass::gemm::GemmShape<64, 64, 16>;
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using InstructionShape = cutlass::gemm::GemmShape<8, 8, 16>;
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using Element = ElementOutput;
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using LayoutA = cutlass::layout::RowMajorTensorOpMultiplicandCrosswise<
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cutlass::sizeof_bits<Element>::value, 64>;
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using LayoutB = cutlass::layout::ColumnMajorTensorOpMultiplicandCrosswise<
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cutlass::sizeof_bits<Element>::value, 64>;
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using WarpMmaTensorOp = typename cutlass::gemm::warp::DefaultMmaTensorOp<
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WarpShape, InstructionShape, Element, LayoutA, Element, LayoutB, ElementAccumulator,
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cutlass::layout::RowMajor, cutlass::arch::OpMultiplyAddSaturate>::Type;
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//
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// Output operator
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//
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using OutputOp = cutlass::epilogue::thread::LinearCombination<
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ElementOutput,
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kElementsPerAccess,
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ElementAccumulator,
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ElementCompute
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>;
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//
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// Define the epilogue
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//
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using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueTensorOp<
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Shape,
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WarpMmaTensorOp,
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kPartitionsK,
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OutputOp,
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kElementsPerAccess
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>::Epilogue;
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//
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// Instantiate epilogue
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//
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EpilogueTestbed<Epilogue> testbed;
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bool passed = testbed.run_all();
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EXPECT_TRUE(passed);
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}
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TEST(SM75_Epilogue_threadblock_epilogue, s8_tensor_op_128x64_64x32x16) {
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//
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@@ -2516,6 +2575,249 @@ TEST(SM75_Epilogue_threadblock_epilogue, f16_tensor_op_128x64_64x32x8) {
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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TEST(SM80_Epilogue_threadblock_epilogue, f64_tensor_op_64x64_32x32x4) {
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//
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// Define the warp-level matrix multiply
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//
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using ElementOutput = double;
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using ElementAccumulator = double;
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using ElementCompute = double;
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int const kElementsPerAccess = 1;
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int const kPartitionsK = 1;
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using Shape = cutlass::gemm::GemmShape<64, 64, 16>;
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using WarpShape = cutlass::gemm::GemmShape<32, 32, 16>;
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using InstructionShape = cutlass::gemm::GemmShape<8, 8, 4>;
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using Element = double;
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using ElementC = ElementAccumulator;
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using LayoutA = cutlass::layout::ColumnMajorTensorOpMultiplicandCongruous64b;
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using LayoutB = cutlass::layout::RowMajorTensorOpMultiplicandCongruous64b;
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using LayoutC = cutlass::layout::RowMajor;
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using WarpMmaTensorOp = typename cutlass::gemm::warp::DefaultMmaTensorOp<
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WarpShape, InstructionShape, Element, LayoutA, Element, LayoutB, ElementC,
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LayoutC>::Type;
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//
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// Output operator
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//
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using OutputOp = cutlass::epilogue::thread::LinearCombination<
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ElementOutput,
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kElementsPerAccess,
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ElementAccumulator,
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ElementCompute
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>;
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//
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// Define the epilogue
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//
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using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueTensorOp<
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Shape,
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WarpMmaTensorOp,
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kPartitionsK,
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OutputOp,
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kElementsPerAccess
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>::Epilogue;
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//
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// Instantiate epilogue
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//
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EpilogueTestbed<Epilogue> testbed;
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bool passed = testbed.run_all();
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EXPECT_TRUE(passed);
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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TEST(SM80_Epilogue_threadblock_epilogue, f64_tensor_op_128x64_64x32x4) {
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//
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// Define the warp-level matrix multiply
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//
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using ElementOutput = double;
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using ElementAccumulator = double;
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using ElementCompute = double;
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int const kElementsPerAccess = 1;
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int const kPartitionsK = 1;
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using Shape = cutlass::gemm::GemmShape<64, 64, 16>;
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using WarpShape = cutlass::gemm::GemmShape<32, 32, 16>;
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using InstructionShape = cutlass::gemm::GemmShape<8, 8, 4>;
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using Element = double;
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using ElementC = ElementAccumulator;
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using LayoutA = cutlass::layout::ColumnMajorTensorOpMultiplicandCongruous64b;
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using LayoutB = cutlass::layout::RowMajorTensorOpMultiplicandCongruous64b;
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using LayoutC = cutlass::layout::RowMajor;
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using WarpMmaTensorOp = typename cutlass::gemm::warp::DefaultMmaTensorOp<
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WarpShape, InstructionShape, Element, LayoutA, Element, LayoutB, ElementC,
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LayoutC>::Type;
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//
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// Output operator
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//
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using OutputOp = cutlass::epilogue::thread::LinearCombination<
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ElementOutput,
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kElementsPerAccess,
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ElementAccumulator,
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ElementCompute
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>;
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//
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// Define the epilogue
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//
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using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueTensorOp<
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Shape,
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WarpMmaTensorOp,
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kPartitionsK,
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OutputOp,
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kElementsPerAccess
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>::Epilogue;
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//
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// Instantiate epilogue
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//
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EpilogueTestbed<Epilogue> testbed;
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bool passed = testbed.run_all();
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EXPECT_TRUE(passed);
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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TEST(SM80_Epilogue_threadblock_epilogue, f64_tensor_op_64x128_32x64x4) {
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//
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// Define the warp-level matrix multiply
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//
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using ElementOutput = double;
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using ElementAccumulator = double;
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using ElementCompute = double;
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int const kElementsPerAccess = 1;
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int const kPartitionsK = 1;
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using Shape = cutlass::gemm::GemmShape<64, 64, 16>;
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using WarpShape = cutlass::gemm::GemmShape<32, 32, 16>;
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using InstructionShape = cutlass::gemm::GemmShape<8, 8, 4>;
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using Element = double;
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using ElementC = ElementAccumulator;
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using LayoutA = cutlass::layout::ColumnMajorTensorOpMultiplicandCongruous64b;
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using LayoutB = cutlass::layout::RowMajorTensorOpMultiplicandCongruous64b;
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using LayoutC = cutlass::layout::RowMajor;
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using WarpMmaTensorOp = typename cutlass::gemm::warp::DefaultMmaTensorOp<
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WarpShape, InstructionShape, Element, LayoutA, Element, LayoutB, ElementC,
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LayoutC>::Type;
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//
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// Output operator
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//
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using OutputOp = cutlass::epilogue::thread::LinearCombination<
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ElementOutput,
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kElementsPerAccess,
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ElementAccumulator,
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ElementCompute
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>;
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//
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// Define the epilogue
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//
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using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueTensorOp<
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Shape,
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WarpMmaTensorOp,
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kPartitionsK,
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OutputOp,
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kElementsPerAccess
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>::Epilogue;
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//
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// Instantiate epilogue
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//
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EpilogueTestbed<Epilogue> testbed;
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bool passed = testbed.run_all();
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EXPECT_TRUE(passed);
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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TEST(SM80_Epilogue_threadblock_epilogue, f64_tensor_op_128x128_32x64x4) {
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//
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// Define the warp-level matrix multiply
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//
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using ElementOutput = double;
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using ElementAccumulator = double;
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using ElementCompute = double;
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int const kElementsPerAccess = 1;
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int const kPartitionsK = 1;
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using Shape = cutlass::gemm::GemmShape<128, 128, 16>;
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using WarpShape = cutlass::gemm::GemmShape<32, 64, 16>;
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using InstructionShape = cutlass::gemm::GemmShape<8, 8, 4>;
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using Element = double;
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using ElementC = ElementAccumulator;
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using LayoutA = cutlass::layout::ColumnMajorTensorOpMultiplicandCongruous64b;
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using LayoutB = cutlass::layout::RowMajorTensorOpMultiplicandCongruous64b;
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using LayoutC = cutlass::layout::RowMajor;
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using WarpMmaTensorOp = typename cutlass::gemm::warp::DefaultMmaTensorOp<
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WarpShape, InstructionShape, Element, LayoutA, Element, LayoutB, ElementC,
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LayoutC>::Type;
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//
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// Output operator
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//
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using OutputOp = cutlass::epilogue::thread::LinearCombination<
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ElementOutput,
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kElementsPerAccess,
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ElementAccumulator,
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ElementCompute
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>;
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//
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// Define the epilogue
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//
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using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueTensorOp<
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Shape,
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WarpMmaTensorOp,
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kPartitionsK,
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OutputOp,
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kElementsPerAccess
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>::Epilogue;
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//
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// Instantiate epilogue
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//
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EpilogueTestbed<Epilogue> testbed;
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bool passed = testbed.run_all();
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EXPECT_TRUE(passed);
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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TEST(SM75_Epilogue_threadblock_epilogue, vec1_mixed_f16_f32_tensor_op_128x128_64x64x8) {
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
|
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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Reference in New Issue
Block a user