3.6.0 update (#2005)
* 3.6.0 update * doc and swap stuff --------- Co-authored-by: yuzhai <yuzhai@nvidia.com> Co-authored-by: Haicheng Wu <haichengw@nvidia.com>
This commit is contained in:
co-authored by
yuzhai
Haicheng Wu
parent
e1cd8c7866
commit
3d261a5974
+13
-13
@@ -39,7 +39,7 @@ namespace cute
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{
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//
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// Direct Copy for any type
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// Direct Copy for any specific types
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//
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template <class S, class D = S>
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@@ -48,21 +48,15 @@ struct UniversalCopy
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using SRegisters = S[1];
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using DRegisters = D[1];
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template <class S_, class D_>
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CUTE_HOST_DEVICE static constexpr void
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copy(S_ const& src,
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D_ & dst)
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{
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dst = static_cast<D>(static_cast<S>(src));
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}
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// Sanity
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static_assert(sizeof_bits_v<S> >= 8);
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static_assert(sizeof_bits_v<D> >= 8);
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// Accept mutable temporaries
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template <class S_, class D_>
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CUTE_HOST_DEVICE static constexpr void
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copy(S_ const& src,
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D_ && dst)
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copy(S const& src,
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D & dst)
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{
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UniversalCopy<S,D>::copy(src, dst);
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dst = src;
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}
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};
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@@ -92,6 +86,12 @@ using AutoVectorizingCopy = AutoVectorizingCopyWithAssumedAlignment<128>;
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using DefaultCopy = AutoVectorizingCopyWithAssumedAlignment<8>;
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//
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// Copy policy automatically selecting between
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// UniversalCopy and cp.async , based on type and memory space.
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//
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struct AutoCopyAsync {};
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//
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// Global memory prefetch into L2
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//
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@@ -2040,6 +2040,103 @@ struct SM80_16x8x64_S32U4U4S32_TN_SATURATE
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 8x8x128 TN
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struct SM80_8x8x128_S32U1U1S32_TN_ANDPOPC
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{
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using DRegisters = uint32_t[2];
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using ARegisters = uint32_t[1];
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using BRegisters = uint32_t[1];
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using CRegisters = uint32_t[2];
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CUTE_HOST_DEVICE static void
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fma(uint32_t & d0, uint32_t & d1,
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uint32_t const& a0,
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uint32_t const& b0,
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uint32_t const& c0, uint32_t const& c1)
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{
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#if defined(CUTE_ARCH_MMA_SM80_ENABLED)
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asm volatile(
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"mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc "
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"{%0, %1},"
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"{%2},"
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"{%3},"
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"{%4, %5};\n"
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: "=r"(d0), "=r"(d1)
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: "r"(a0),
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"r"(b0),
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"r"(c0), "r"(c1));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM80_8x8x128_S32U1U1S32_TN_ANDPOPC without CUTE_ARCH_MMA_SM80_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x128 TN
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struct SM80_16x8x128_S32U1U1S32_TN_ANDPOPC
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{
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using DRegisters = uint32_t[4];
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using ARegisters = uint32_t[2];
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using BRegisters = uint32_t[1];
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using CRegisters = uint32_t[4];
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CUTE_HOST_DEVICE static void
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fma(uint32_t & d0, uint32_t & d1, uint32_t & d2, uint32_t & d3,
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uint32_t const& a0, uint32_t const& a1,
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uint32_t const& b0,
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uint32_t const& c0, uint32_t const& c1, uint32_t const& c2, uint32_t const& c3)
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{
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#if defined(CUTE_ARCH_MMA_SM80_ENABLED)
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asm volatile(
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"mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc "
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"{%0, %1, %2, %3},"
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"{%4, %5},"
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"{%6},"
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"{%7, %8, %9, %10};\n"
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: "=r"(d0), "=r"(d1), "=r"(d2), "=r"(d3)
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: "r"(a0), "r"(a1),
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"r"(b0),
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"r"(c0), "r"(c1), "r"(c2), "r"(c3));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM80_16x8x128_S32U1U1S32_TN_ANDPOPC without CUTE_ARCH_MMA_SM80_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x256 TN
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struct SM80_16x8x256_S32U1U1S32_TN_ANDPOPC
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{
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using DRegisters = uint32_t[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[2];
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using CRegisters = uint32_t[4];
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CUTE_HOST_DEVICE static void
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fma(uint32_t & d0, uint32_t & d1, uint32_t & d2, uint32_t & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1,
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uint32_t const& c0, uint32_t const& c1, uint32_t const& c2, uint32_t const& c3)
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{
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#if defined(CUTE_ARCH_MMA_B1_AND_SM80_ENABLED)
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asm volatile(
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"mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9},"
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"{%10, %11, %12, %13};\n"
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: "=r"(d0), "=r"(d1), "=r"(d2), "=r"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1),
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"r"(c0), "r"(c1), "r"(c2), "r"(c3));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM80_16x8x256_S32U1U1S32_TN_ANDPOPC without CUTE_ARCH_MMA_SM80_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 8x8x128 TN
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@@ -2141,103 +2238,4 @@ struct SM80_16x8x256_S32U1U1S32_TN_XORPOPC
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 8x8x128 TN
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struct SM80_8x8x128_S32U1U1S32_TN_ANDPOPC
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{
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using DRegisters = uint32_t[2];
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using ARegisters = uint32_t[1];
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using BRegisters = uint32_t[1];
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using CRegisters = uint32_t[2];
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CUTE_HOST_DEVICE static void
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fma(uint32_t & d0, uint32_t & d1,
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uint32_t const& a0,
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uint32_t const& b0,
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uint32_t const& c0, uint32_t const& c1)
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{
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#if defined(CUTE_ARCH_MMA_B1_AND_SM80_ENABLED)
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asm volatile(
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"mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.and.popc "
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"{%0, %1},"
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"{%2},"
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"{%3},"
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"{%4, %5};\n"
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: "=r"(d0), "=r"(d1)
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: "r"(a0),
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"r"(b0),
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"r"(c0), "r"(c1));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM80_8x8x128_S32U1U1S32_TN_ANDPOPC without CUTE_ARCH_MMA_SM80_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x128 TN
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struct SM80_16x8x128_S32U1U1S32_TN_ANDPOPC
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{
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using DRegisters = uint32_t[4];
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using ARegisters = uint32_t[2];
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using BRegisters = uint32_t[1];
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using CRegisters = uint32_t[4];
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CUTE_HOST_DEVICE static void
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fma(uint32_t & d0, uint32_t & d1, uint32_t & d2, uint32_t & d3,
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uint32_t const& a0, uint32_t const& a1,
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uint32_t const& b0,
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uint32_t const& c0, uint32_t const& c1, uint32_t const& c2, uint32_t const& c3)
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{
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#if defined(CUTE_ARCH_MMA_B1_AND_SM80_ENABLED)
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asm volatile(
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"mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc "
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"{%0, %1, %2, %3},"
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"{%4, %5},"
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"{%6},"
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"{%7, %8, %9, %10};\n"
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: "=r"(d0), "=r"(d1), "=r"(d2), "=r"(d3)
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: "r"(a0), "r"(a1),
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"r"(b0),
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"r"(c0), "r"(c1), "r"(c2), "r"(c3));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM80_16x8x128_S32U1U1S32_TN_ANDPOPC without CUTE_ARCH_MMA_SM80_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// MMA 16x8x256 TN
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struct SM80_16x8x256_S32U1U1S32_TN_ANDPOPC
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{
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using DRegisters = uint32_t[4];
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using ARegisters = uint32_t[4];
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using BRegisters = uint32_t[2];
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using CRegisters = uint32_t[4];
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CUTE_HOST_DEVICE static void
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fma(uint32_t & d0, uint32_t & d1, uint32_t & d2, uint32_t & d3,
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uint32_t const& a0, uint32_t const& a1, uint32_t const& a2, uint32_t const& a3,
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uint32_t const& b0, uint32_t const& b1,
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uint32_t const& c0, uint32_t const& c1, uint32_t const& c2, uint32_t const& c3)
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{
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#if defined(CUTE_ARCH_MMA_B1_AND_SM80_ENABLED)
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asm volatile(
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"mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc "
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"{%0, %1, %2, %3},"
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"{%4, %5, %6, %7},"
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"{%8, %9},"
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"{%10, %11, %12, %13};\n"
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: "=r"(d0), "=r"(d1), "=r"(d2), "=r"(d3)
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: "r"(a0), "r"(a1), "r"(a2), "r"(a3),
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"r"(b0), "r"(b1),
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"r"(c0), "r"(c1), "r"(c2), "r"(c3));
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#else
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CUTE_INVALID_CONTROL_PATH("Attempting to use SM80_16x8x256_S32U1U1S32_TN_ANDPOPC without CUTE_ARCH_MMA_SM80_ENABLED");
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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} // namespace cute
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