cutlass 3.9 update (#2255)

* cutlass 3.9 update

* rebase

* fixes out of shared memory for blockwise Blackwell

* doc format

* fix issue 2253

* disable host ref by default

* fix sm120 smem capacity

---------

Co-authored-by: yuzhai <yuzhai@nvidia.com>
Co-authored-by: Haicheng Wu <haichengw@nvidia.com>

include/cute/arch/tmem_allocator_sm100.hpp

@@ -28,19 +28,34 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  **************************************************************************************************/
-//
 
-//
 #pragma once
 
 #include <cute/arch/config.hpp>
-#include <cute/arch/cluster_sm90.hpp>
-#include <cute/atom/copy_traits_sm100.hpp>
-
-#include <cutlass/pipeline/sm90_pipeline.hpp>
+#include <cute/arch/util.hpp>
+#include <cute/numeric/integral_constant.hpp>
+#include <cute/pointer.hpp>
 
 namespace cute::TMEM {
 
+//
+// TMEM Addressing Constants
+//
+
+// 128 DP x 512 COL x uint32_t-addressing
+using MAX_CAPACITY_BITS = Int<128*512*32>;
+
+// TMEM DP stride in bit-addressing (shift by 5 for conversion from uint32_t)
+using DP_b = cute::constant<int32_t, (1 << 21)>;
+
+// TMEM DP stride in type-T addressing
+template <class T = uint32_t>
+using DP = cute::constant<int32_t, shiftl((1 << 16), tmem_ptr<T>::OffsetShift)>;
+
+//
+// TMEM Allocators
+//
+
 // All operations of this class require that only a single warp uniformly participates
 class Allocator1Sm {
 public:
@@ -77,8 +92,8 @@ public:
     asm volatile(
       "{\n\t"
       "tcgen05.dealloc.cta_group::1.sync.aligned.b32  %0, %1; \n\t"
-      "}" 
-      : 
+      "}"
+      :
       : "r"(tmem_ptr), "r"(num_columns));
   #else
     CUTE_INVALID_CONTROL_PATH("Attempting to use TMEM allocation PTX without CUTE_ARCH_TCGEN05_TMEM_ENABLED");
@@ -130,7 +145,7 @@ public:
   }
 
   /**
-   * Frees the TMEM corresponding to the pointer and slice count provided. 
+   * Frees the TMEM corresponding to the pointer and slice count provided.
    * Release the TMEM after checking that the CTA issuing the free does indeed own the corresponding slices.
    * @param tmem_ptr Base address of the TMEM address space being freed.
    * @param num_columns Number of columns being freed. Must be 32 <= num_columns <= 512 and power of 2.
@@ -146,8 +161,8 @@ public:
     asm volatile(
       "{\n\t"
       "tcgen05.dealloc.cta_group::2.sync.aligned.b32  %0, %1; \n\t"
-      "}" 
-      : 
+      "}"
+      :
       : "r"(tmem_ptr), "r"(num_columns));
   #else
     CUTE_INVALID_CONTROL_PATH("Attempting to use TMEM allocation PTX without CUTE_ARCH_TCGEN05_TMEM_ENABLED");