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CUTLASS 2.7 (#318)

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CUTLASS 2.7

Mainloop fusion for GEMM: summation over A or B
Strided DGRAD (optimized iterators)
Half-precision GELU_taylor activation functions
Use these when accumulation and epilogue compute types are all cutlass::half_t
Tuning and bug fixes to fused GEMM + GEMM example
Support for smaller than 128b aligned Convolutions: see examples
Caching of results to accelerate Convolution unit tests
Can be enabled or disabled by running cmake .. -DCUTLASS_TEST_ENABLE_CACHED_RESULTS=OFF
Corrections and bug fixes reported by the CUTLASS community
Thank you for filing these issues!

authored-by: Haicheng Wu haichengw@nvidia.com, Manish Gupta manigupta@nvidia.com, Dustyn Blasig dblasig@nvidia.com, Andrew Kerr akerr@nvidia.com
This commit is contained in:
Manish Gupta
2021-09-20 11:02:22 -07:00
committed by GitHub
parent 9ac255863f
commit 2e07c4cc2f
62 changed files with 5611 additions and 186 deletions
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test/unit/conv/device/CMakeLists.txt
+11 -12
View File
@@ -134,7 +134,7 @@ cutlass_test_unit_add_executable(
conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm70.cu
)
# Conv2d - F16 input, F32 output, F32 accumulation - SM75
# Conv - F16 input, F32 output, F32 accumulation - SM75
cutlass_test_unit_add_executable(
cutlass_test_unit_conv_device_tensorop_f32_sm75
@@ -144,11 +144,13 @@ cutlass_test_unit_add_executable(
conv2d_fprop_with_broadcast_sm75.cu
conv2d_fprop_with_reduction_sm75.cu
conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm75.cu
)
if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 80)
# Conv2d - F16 input, F16 output, F16 accumulation
# Conv - F16 input, F16 output, F16 accumulation
cutlass_test_unit_add_executable(
cutlass_test_unit_conv_device_tensorop_f16_sm80
@@ -157,24 +159,23 @@ if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 80)
conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f16nhwc_tensor_op_f16_sm80.cu
)
# Conv2d - F16 input, F32 output, F32 accumulation
# Conv - F16 input, F32 output, F32 accumulation
cutlass_test_unit_add_executable(
cutlass_test_unit_conv_device_tensorop_f32_sm80
# Conv2d
conv2d_fprop_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
conv2d_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
conv2d_wgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm75.cu
conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
# Strided Dgrad
# Conv2d (Strided Dgrad)
conv2d_strided_dgrad_implicit_gemm_f16nhwc_f16nhwc_f32nhwc_tensor_op_f32_sm80.cu
# Conv3d
conv3d_wgrad_implicit_gemm_f16ndhwc_f16ndhwc_f32ndhwc_tensor_op_f32_sm80.cu
)
# Conv2d - TF32 input, F32 output, F32 accumulation
# Conv - TF32 input, F32 output, F32 accumulation
cutlass_test_unit_add_executable(
cutlass_test_unit_conv_device_tensorop_f32_tf32_sm80
@@ -192,7 +193,6 @@ endif()
if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 75)
# Conv2d - S8 input, S32 output, S32 accumulation
cutlass_test_unit_add_executable(
cutlass_test_unit_conv_device_tensorop_s32
conv2d_fprop_implicit_gemm_s8nhwc_s8nhwc_s32nhwc_tensor_op_s32_sm75.cu
@@ -200,7 +200,6 @@ if (CUTLASS_NVCC_MAX_ARCH GREATER_EQUAL 75)
)
# Conv2d - S8 interleaved input, S8 interleaved output, S32 accumulation
cutlass_test_unit_add_executable(
cutlass_test_unit_conv_device_tensorop_s32_interleaved
conv2d_fprop_implicit_gemm_s8ncxhwx_s8cxrskx_s8ncxhwx_tensor_op_s32_sm75.cu