CUTLASS 2.5
This commit is contained in:
@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -111,9 +111,7 @@ template <
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/// epilogue
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bool SplitKSerial,
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/// Operation performed by GEMM
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typename Operator,
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/// Beta is zero or not
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bool IsBetaZero = false>
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typename Operator>
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struct DefaultGemm;
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////////////////////////////////////////////////////////////////////////////////
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@@ -295,16 +293,14 @@ template <
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/// epilogue
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bool SplitKSerial,
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/// Operation performed by GEMM
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typename Operator,
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/// Is Beta zero or not
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bool IsBetaZero>
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typename Operator>
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struct DefaultGemm<
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ElementA, layout::ColumnMajorInterleaved<InterleavedK>, kAlignmentA,
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ElementB, layout::RowMajorInterleaved<InterleavedK>, kAlignmentB, ElementC,
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layout::ColumnMajorInterleaved<InterleavedK>, int32_t,
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arch::OpClassTensorOp, arch::Sm80, ThreadblockShape, WarpShape,
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InstructionShape, EpilogueOutputOp, ThreadblockSwizzle, Stages,
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SplitKSerial, Operator, IsBetaZero> {
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SplitKSerial, Operator> {
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using LayoutA = layout::ColumnMajorInterleaved<InterleavedK>;
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using LayoutB = layout::RowMajorInterleaved<InterleavedK>;
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using LayoutC = layout::ColumnMajorInterleaved<InterleavedK>;
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@@ -324,8 +320,7 @@ struct DefaultGemm<
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using Epilogue = typename cutlass::epilogue::threadblock::
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DefaultInterleavedEpilogueTensorOp<
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ThreadblockShape, typename Mma::Operator, kPartitionsK, EpilogueOutputOp,
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64 / sizeof_bits<ElementC>::value, InterleavedK,
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IsBetaZero>::Epilogue;
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64 / sizeof_bits<ElementC>::value, InterleavedK>::Epilogue;
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/// Define the kernel-level GEMM operator.
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using GemmKernel = kernel::Gemm<Mma, Epilogue, ThreadblockSwizzle, SplitKSerial>;
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@@ -361,16 +356,14 @@ template <
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/// epilogue
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bool SplitKSerial,
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/// Operation performed by GEMM
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typename Operator,
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/// Is Beta zero or not
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bool IsBetaZero>
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typename Operator>
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struct DefaultGemm<ElementA, layout::ColumnMajorInterleaved<InterleavedK>,
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kAlignmentA, ElementB,
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layout::RowMajorInterleaved<InterleavedK>, kAlignmentB,
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ElementC, layout::ColumnMajorInterleaved<InterleavedK>,
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int32_t, arch::OpClassTensorOp, arch::Sm75, ThreadblockShape,
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WarpShape, InstructionShape, EpilogueOutputOp,
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ThreadblockSwizzle, 2, SplitKSerial, Operator, IsBetaZero> {
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ThreadblockSwizzle, 2, SplitKSerial, Operator> {
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using LayoutA = layout::ColumnMajorInterleaved<InterleavedK>;
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using LayoutB = layout::RowMajorInterleaved<InterleavedK>;
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using LayoutC = layout::ColumnMajorInterleaved<InterleavedK>;
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@@ -389,8 +382,7 @@ struct DefaultGemm<ElementA, layout::ColumnMajorInterleaved<InterleavedK>,
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using Epilogue = typename cutlass::epilogue::threadblock::
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DefaultInterleavedEpilogueTensorOp<
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ThreadblockShape, typename Mma::Operator, kPartitionsK, EpilogueOutputOp,
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64 / sizeof_bits<ElementC>::value, InterleavedK,
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IsBetaZero>::Epilogue;
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64 / sizeof_bits<ElementC>::value, InterleavedK>::Epilogue;
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/// Define the kernel-level GEMM operator.
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using GemmKernel = kernel::Gemm<Mma, Epilogue, ThreadblockSwizzle, SplitKSerial>;
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@@ -682,7 +674,7 @@ struct DefaultGemm<int8_t, LayoutA, kAlignmentA, int8_t, LayoutB, kAlignmentB,
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ElementC, LayoutC, ElementAccumulator, arch::OpClassSimt,
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ArchTag, ThreadblockShape, WarpShape, GemmShape<1, 1, 4>,
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EpilogueOutputOp, ThreadblockSwizzle, 2, SplitKSerial,
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Operator, false> {
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Operator> {
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using InstructionShape = GemmShape<1, 1, 4>;
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using ElementA = int8_t;
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using ElementB = int8_t;
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@@ -703,8 +695,7 @@ struct DefaultGemm<int8_t, LayoutA, kAlignmentA, int8_t, LayoutB, kAlignmentB,
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WarpShape,
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InstructionShape,
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2,
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Operator,
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false
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Operator
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>::ThreadblockMma;
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static int const kEpilogueElementsPerAccess = EpilogueOutputOp::kCount;
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
|
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -112,9 +112,7 @@ template <
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/// epilogue
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bool SplitKSerial,
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/// Operation performed by GEMM
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typename Operator,
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/// Beta is zero or not
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bool IsBetaZero = false>
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typename Operator>
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struct DefaultSparseGemm;
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////////////////////////////////////////////////////////////////////////////////
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -1,5 +1,5 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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@@ -185,8 +185,7 @@ struct DefaultGemmUniversal<
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ThreadblockSwizzle,
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Stages,
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true,
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Operator,
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false
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Operator
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>::GemmKernel;
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/// Define the kernel in terms of the default kernel
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@@ -0,0 +1,240 @@
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/***************************************************************************************************
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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||||
* provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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/*! \file
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\brief
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Defines a GEMM with Reduction based on an existing UniversalGemm kernel.
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*/
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#pragma once
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#include "cutlass/cutlass.h"
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#include "cutlass/gemm/kernel/gemm_with_fused_epilogue.h"
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#include "cutlass/gemm/kernel/default_gemm_universal.h"
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#include "cutlass/epilogue/threadblock/default_epilogue_with_reduction.h"
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#include "cutlass/epilogue/threadblock/epilogue_with_reduction.h"
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/////////////////////////////////////////////////////////////////////////////////////////////////
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namespace cutlass {
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namespace gemm {
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namespace kernel {
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/////////////////////////////////////////////////////////////////////////////////////////////////
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template <
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/// Element type for A matrix operand
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typename ElementA_,
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/// Layout type for A matrix operand
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typename LayoutA_,
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/// Complex elementwise transformation on A operand
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ComplexTransform TransformA,
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/// Access granularity of A matrix in units of elements
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int kAlignmentA,
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/// Element type for B matrix operand
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typename ElementB_,
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/// Layout type for B matrix operand
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typename LayoutB_,
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/// Complex elementwise transformation on B operand
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ComplexTransform TransformB,
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/// Access granularity of B matrix in units of elements
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int kAlignmentB,
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/// Element type for C and D matrix operands
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typename ElementC_,
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/// Layout type for C and D matrix operands
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typename LayoutC_,
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/// Element type for internal accumulation
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typename ElementAccumulator,
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/// Operator class tag
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typename OperatorClass,
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/// Tag indicating architecture to tune for
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typename ArchTag,
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/// Threadblock-level tile size (concept: GemmShape)
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typename ThreadblockShape,
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/// Warp-level tile size (concept: GemmShape)
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typename WarpShape,
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/// Warp-level tile size (concept: GemmShape)
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typename InstructionShape,
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/// Epilogue output operator
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typename EpilogueOutputOp,
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/// Epilogue reduction operator
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typename EpilogueReductionOp,
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/// Threadblock-level swizzling operator
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typename ThreadblockSwizzle,
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/// Number of stages used in the pipelined mainloop
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int Stages,
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/// Operation performed by GEMM
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typename Operator,
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///
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typename Enable = void
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>
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struct DefaultGemmWithReduction {
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using GemmBase = typename DefaultGemmUniversal<
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ElementA_, LayoutA_, TransformA, kAlignmentA,
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ElementB_, LayoutB_, TransformB, kAlignmentB,
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ElementC_, LayoutC_, ElementAccumulator,
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OperatorClass,
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ArchTag,
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ThreadblockShape,
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WarpShape,
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InstructionShape,
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EpilogueOutputOp,
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ThreadblockSwizzle,
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Stages,
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Operator
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>::GemmKernel;
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// Replace epilogue
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using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueWithReductionTensorOp<
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typename GemmBase::Epilogue::Shape,
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typename GemmBase::Epilogue::WarpMmaOperator,
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GemmBase::Epilogue::kPartitionsK,
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ElementC_,
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EpilogueOutputOp,
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EpilogueReductionOp,
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GemmBase::Epilogue::kElementsPerAccess
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>::Epilogue;
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// Compose the GEMM kernel
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using GemmKernel = GemmWithFusedEpilogue<
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typename GemmBase::Mma,
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Epilogue,
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ThreadblockSwizzle
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>;
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};
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/////////////////////////////////////////////////////////////////////////////////////////////////
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/// Parital specialization: ArchTag = cutlass::arch::Sm70
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///
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///
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template <
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/// Element type for A matrix operand
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typename ElementA_,
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/// Layout type for A matrix operand
|
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typename LayoutA_,
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/// Complex elementwise transformation on A operand
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ComplexTransform TransformA,
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/// Access granularity of A matrix in units of elements
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int kAlignmentA,
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/// Element type for B matrix operand
|
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typename ElementB_,
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/// Layout type for B matrix operand
|
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typename LayoutB_,
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/// Complex elementwise transformation on B operand
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ComplexTransform TransformB,
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/// Access granularity of B matrix in units of elements
|
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int kAlignmentB,
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/// Element type for C and D matrix operands
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typename ElementC_,
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/// Layout type for C and D matrix operands
|
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typename LayoutC_,
|
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/// Element type for internal accumulation
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typename ElementAccumulator,
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/// Operator class tag
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||||
typename OperatorClass,
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/// Threadblock-level tile size (concept: GemmShape)
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typename ThreadblockShape,
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/// Warp-level tile size (concept: GemmShape)
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typename WarpShape,
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/// Warp-level tile size (concept: GemmShape)
|
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typename InstructionShape,
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/// Epilogue output operator
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typename EpilogueOutputOp,
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/// Epilogue reduction operator
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typename EpilogueReductionOp,
|
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/// Threadblock-level swizzling operator
|
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typename ThreadblockSwizzle,
|
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/// Number of stages used in the pipelined mainloop
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int Stages,
|
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/// Operation performed by GEMM
|
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typename Operator,
|
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///
|
||||
typename Enable
|
||||
>
|
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struct DefaultGemmWithReduction<
|
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ElementA_, LayoutA_, TransformA, kAlignmentA,
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ElementB_, LayoutB_, TransformB, kAlignmentB,
|
||||
ElementC_, LayoutC_,
|
||||
ElementAccumulator,
|
||||
OperatorClass,
|
||||
cutlass::arch::Sm70,
|
||||
ThreadblockShape,
|
||||
WarpShape,
|
||||
InstructionShape,
|
||||
EpilogueOutputOp,
|
||||
EpilogueReductionOp,
|
||||
ThreadblockSwizzle,
|
||||
Stages,
|
||||
Operator,
|
||||
Enable
|
||||
> {
|
||||
|
||||
using GemmBase = typename DefaultGemmUniversal<
|
||||
ElementA_, LayoutA_, TransformA, kAlignmentA,
|
||||
ElementB_, LayoutB_, TransformB, kAlignmentB,
|
||||
ElementC_, LayoutC_, ElementAccumulator,
|
||||
OperatorClass,
|
||||
cutlass::arch::Sm70,
|
||||
ThreadblockShape,
|
||||
WarpShape,
|
||||
InstructionShape,
|
||||
EpilogueOutputOp,
|
||||
ThreadblockSwizzle,
|
||||
Stages,
|
||||
Operator
|
||||
>::GemmKernel;
|
||||
|
||||
// Replace epilogue
|
||||
using Epilogue = typename cutlass::epilogue::threadblock::DefaultEpilogueWithReductionVoltaTensorOp<
|
||||
typename GemmBase::Epilogue::Shape,
|
||||
typename GemmBase::Epilogue::WarpMmaOperator,
|
||||
GemmBase::Epilogue::kPartitionsK,
|
||||
ElementC_,
|
||||
EpilogueOutputOp,
|
||||
EpilogueReductionOp,
|
||||
GemmBase::Epilogue::kElementsPerAccess
|
||||
>::Epilogue;
|
||||
|
||||
// Compose the GEMM kernel
|
||||
using GemmKernel = GemmWithFusedEpilogue<
|
||||
typename GemmBase::Mma,
|
||||
Epilogue,
|
||||
ThreadblockSwizzle
|
||||
>;
|
||||
};
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
} // namespace kernel
|
||||
} // namespace gemm
|
||||
} // namespace cutlass
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/***************************************************************************************************
|
||||
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
Reference in New Issue
Block a user