 sogalinandHubert Lu
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8d114f254b
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Fix RMSNorm API CALL mismatch issue. (#10032)
Co-authored-by: Hubert Lu <Hubert.Lu@amd.com>
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2025-09-05 20:45:13 -07:00 |
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VDV1985
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ba861293cf
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[feat]Ascend NPU Gemma-3-12b and Gemma-3-27b support (#8909)
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2025-08-31 00:25:07 -07:00 |
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strgrbandZhang Kaihong
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88fbc31b50
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Support trtllm_allreduce_fusion in flashinfer for cuda<12.8 (#9339)
Co-authored-by: Zhang Kaihong <zhangkaihong.zkh@alibaba-inc.com>
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2025-08-20 16:54:30 -07:00 |
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b7094a5ef1
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model: support intern-s1 (#8350)
Signed-off-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: zxy <zhou0493@e.ntu.edu.sg>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Mick <mickjagger19@icloud.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2025-07-26 13:48:51 -07:00 |
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Xiaoyu Zhang
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2e7ab862e3
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Fix illegal memory in trtllm allreduce fusion (#7864)
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2025-07-08 11:47:17 -07:00 |
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Xiaoyu Zhang
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8e64140e35
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[b200] support trt-llm allreduce fuse rms_norm_add kernel (#7621)
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2025-07-02 19:36:20 -07:00 |
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ll819214andLi Junwen
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506a2d5934
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npu fused op (#7386)
Co-authored-by: Li Junwen <lijunwen13@hisilicon.com>
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2025-06-25 01:54:20 -07:00 |
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094c116f7d
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Update python API of activation, topk, norm and rope and remove vllm dependency (#6614)
Co-authored-by: Wu, Chunyuan <chunyuan.wu@intel.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
Co-authored-by: sdp <sdp@gnr799219.jf.intel.com>
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2025-06-17 22:11:50 -07:00 |
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Yijie Zhuand刁莹煜
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a39d928782
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support qwen2 running on ascend npu device (#7022)
Co-authored-by: 刁莹煜 <diaoyingyu1@hisilicon.com>
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2025-06-17 11:24:10 -07:00 |
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b819381fec
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AITER backend extension and workload optimizations (#6838)
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Hubert Lu <Hubert.Lu@amd.com>
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2025-06-05 23:00:18 -07:00 |
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JieXin Liang
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180ff5eecc
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[fix] recover auto-dispatch for rmsnorm and rope (#6745)
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2025-06-03 21:44:20 -07:00 |
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applesaucethebunandBrayden Zhong
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2ce8793519
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Add typo checker in pre-commit (#6179)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
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2025-05-11 12:55:00 +08:00 |
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michael-amdandispobock
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93c6fb12c7
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Fix: deepseek forward absorb (#5723)
Co-authored-by: ispobock <ispobaoke@163.com>
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2025-04-25 13:48:55 -07:00 |
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HAI
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b0feda090c
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Revert "Support aiter RMSNorm in AMD" (#5646)
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2025-04-22 15:20:24 -07:00 |
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michael-amdandJieXin Liang
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968ef51562
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Support aiter RMSNorm in AMD (#5510)
Co-authored-by: JieXin Liang <Alcanderian@users.noreply.github.com>
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2025-04-21 17:40:39 -07:00 |
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JieXin Liang
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97cb762bb6
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[misc] remove is_cuda_available (#5319)
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2025-04-20 18:16:51 -07:00 |
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Lianmin Zheng
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177320a582
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Clean up imports (#5467)
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2025-04-16 15:26:49 -07:00 |
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Mick
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9d02bb3e2a
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Urgent model support: support gemma-3-it (#4424)
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2025-03-16 17:37:32 -07:00 |
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Yineng Zhang
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65b7c9b78f
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cleanup deps 2/n (#4464)
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2025-03-15 23:06:17 -07:00 |
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ac2387279e
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Support penalty in overlap mode; return logprob with chunked prefill; improve benchmark scripts (#3988)
Co-authored-by: SangBin Cho <rkooo567@gmail.com>
Co-authored-by: dhou-xai <dhou@x.ai>
Co-authored-by: Hanming Lu <hanming_lu@berkeley.edu>
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2025-03-03 00:12:04 -08:00 |
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Yineng Zhang
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4eb4b401cc
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update and simplify CustomOp (#3249)
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2025-02-01 18:56:44 +08:00 |
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Yineng Zhang
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2f79f58873
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feat: use sgl-kernel 0.0.3 in sglang (#3179)
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2025-01-27 21:39:52 +08:00 |
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Xuehai Pan
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62a4a339eb
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docs: fix module docstrings and copyright headers (#2077)
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2024-11-22 22:16:53 +08:00 |
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Yineng Zhang
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766192610e
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feat: update torch 2.5.1 (#2069)
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2024-11-18 21:29:13 +08:00 |
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Lianmin Zheng
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c1f401fc58
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Revert "chore: update torch v2.5.1" (#2063)
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2024-11-17 15:29:38 -08:00 |
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Yineng Zhang
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3b878863f7
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chore: update torch v2.5.1 (#1849)
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2024-11-18 00:06:00 +08:00 |
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Lianmin ZhengandZhang Liangang
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6a5b352aaf
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Use is_flashinfer_available to replace is_hip for flashinfer check (#1596)
Co-authored-by: Zhang Liangang <liangang.zhang@intel.com>
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2024-10-06 22:54:05 -07:00 |
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HAI
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aa2750beb3
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[Bugfix] Enable SGLang on AMD GPUs via PyTorch for ROCm (#1419) (#1453)
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2024-09-18 02:01:35 -07:00 |
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HAI
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3a6e04185b
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[Feature, Hardware] Enable SGLang on AMD GPUs via PyTorch for ROCm (#1420)
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2024-09-17 07:43:52 +00:00 |
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Yineng Zhang
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b1a540ec42
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feat: update GemmaRMSNorm (#1232)
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2024-08-28 22:47:34 +10:00 |
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Yineng Zhang
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198974cd1a
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feat: support sm75 with FlashInfer v0.1.6 (#1233)
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2024-08-28 18:39:12 +10:00 |
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Yineng Zhang
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1fb9459908
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fix: custom op fallback forward native when lower sm80 (#1177)
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2024-08-21 14:26:35 -07:00 |
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Lianmin Zheng
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fb1f28cbbb
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Clean up the comments and names under python/sglang/srt/layers (#1047)
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2024-08-12 05:54:37 +00:00 |
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Yineng Zhang
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c245b78973
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hotfix: add CustomOp abstraction (#1027)
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2024-08-11 02:45:59 -07:00 |
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Yineng Zhang
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94752ac811
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feat: use FlashInfer rmsnorm and silu (#907)
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2024-08-11 14:57:13 +10:00 |
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