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109 Commits
Author SHA1 Message Date
Yuan Luoandluoyuan.luo 4ea4f2a20c [VLM] Optimize get_rope_index for GLM4v (#17420) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
 2026-02-01 18:59:15 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 858dc80aff [Intel GPU] fix device in DeepseekScalingRotaryEmbedding to run DeepSeek-V2-Lite BF16 on XPU (#10021) 
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
 2026-01-29 21:21:38 -08:00
R0CKSTAR d3cdee0a04 [MUSA][4/N] Add common device utilities, distributed backend, and custom op wiring (#17246) 
Signed-off-by: Xiaodong Ye <xiaodong.ye@mthreads.com>
 2026-01-28 23:13:24 -08:00
CSWYF3634076 1a19b3987d [Model] Add Ernie4.5 VL model support (#15679) 
Signed-off-by: CSWYF3634076 <wangyafeng@baidu.com>
Signed-off-by: wangyafeng <wangyafeng@baidu.com>
 2026-01-25 22:36:29 -08:00
McZyWu 8a5ed2434f [NPU]support model MiniCPM3-4B for npu (#16866) 2026-01-24 08:25:12 +08:00
chenxu214amote-icy
 		5d299c25c0 [NPU] bugfix with Kimi-k2 and bge-reranker-v2 model (#17478) 
Co-authored-by: amote-i <49533125+amote-i@users.noreply.github.com>
Co-authored-by: cy <chenyang08056032@163.com>
 2026-01-22 22:02:05 +08:00
Yibo Cai 2f4a6addf3 [cpu/arm64] support run sglang on arm64 cpu (#14867) 2026-01-11 04:27:19 -08:00
chenxu214 7dd679cbb9 [NPU][Bugfix] Fix qwen3 error when enable-dp-lm-head (#16115) 2026-01-08 15:15:43 +08:00
Siyuan ChenandXinyuan Tong 9a414b164c [Performance] Optimze the performance of Qwen25VL (#15640) 
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
 2026-01-02 23:15:36 -08:00
Nan JiangandXinyuan Tong 7254986342 [VLM] feat: true on policy for vlm + fsdp (#14636) 
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
 2026-01-01 16:54:39 -08:00
cen121212 25b48564c3 [NPU][Bugfix] fix Qwen3-VL-30B-A3B-Instruct accuracy loss (#15597) 2025-12-31 15:57:38 +08:00
DarkSharpness 45f3ad2f52 [Refactor] Rename CustomOp -> MultiPlatformOp (#16175) 2025-12-31 01:16:32 +08:00
Liangsheng Yin 374ad4cce0 Fix gpt-oss yarn with truncate argument (#14270) 2025-12-18 16:31:15 +08:00
Yuan Luoandluoyuan.luo 8fa3dc36c5 [VLM] Support cos sin cache for Qwen3-VL & GLM-4.1V (#15205) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
 2025-12-18 08:39:50 +08:00
Liangsheng Yin 0c00220795 tiny unify environ usage (#15335) 2025-12-17 23:31:43 +08:00
XDaoHongandZhengdQin 4733fcff1f [Feature] npu support enable_torch_compile for torchair backend (#13410) 
Co-authored-by: ZhengdQin <zhengdqin@gmail.com>
 2025-12-16 09:23:51 +08:00
DarkSharpness f03bfa4ce3 [Feature] Fuse mrope all in 1 kernel (#14906) 2025-12-15 02:50:55 -08:00
liupeng374 d36299ad77 [NPU] perf update with kvcache nz & w4a8 quant (#14423) 2025-12-13 17:39:55 +08:00
Qiaolin Yu 77873343c4 tiny update: use rope kernel in sgl-kernel for amd (#14955) 2025-12-12 18:48:12 -08:00
yudian0504andluoyuan.luo 9496f12d00 [Model] Add PaddleOCR-VL Model Support (#12953) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
 2025-12-09 10:16:02 -08:00
Qiaolin Yu 661e9775d0 [2/2] Add rope kernel in sgl-kernel (#14452) 2025-12-07 21:37:29 -08:00
LiwansiandEven Zhou 432ecf841e [Ascend] qwen optimization (#12078) 
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
 2025-11-25 19:44:24 +08:00
YAMY 98b38de3f2 Fix: Safe RoPE Cache Expansion to Prevent Position-ID Out-of-Bounds in EAGLE + Long-Sequence Workloads (#11871) 2025-11-25 01:19:06 +08:00
Lianmin Zheng a352e833c4 CI: Kill zombie diffusion processes in CI & minor code style fix on rotary embedding fallback (#13637) 2025-11-20 21:57:01 +08:00
iLeGend 10e0b83a4c Add FP32 dtype support for RoPE - Part2 (#13328) 2025-11-19 21:19:53 -08:00
Yuan Luoluoyuan.luoYuhao Yang
 		af6bcadcf7 [VLM] Support Piecewise CUDA Graph for Qwen2.5-VL (#13055) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
Co-authored-by: Yuhao Yang <yhyang201@gmail.com>
 2025-11-20 10:23:44 +08:00
DarkSharpness f969664172 [Performance] Move the contiguous to torch compile region (#13199) 2025-11-15 20:49:52 -08:00
Makcum888eronnie_zhengssshinigami
 		c2e56dadb2 [Ascend] torch_npu.npu_mrope for MRotaryEmbedding (#10907) 
Co-authored-by: ronnie_zheng <zl19940307@163.com>
Co-authored-by: ssshinigami <44640852+ssshinigami@users.noreply.github.com>
 2025-11-12 21:45:54 +08:00
Ke Bao db24d34603 Support piecewise cuda graph for MLA (#11812) 2025-11-10 09:13:48 +08:00
Lianmin Zhenggithub-actions[bot] <github-actions[bot]@users.noreply.github.com>Stefan He
 		0296f1cdad [Auto Sync] Update activation.py, logits_processor.py, rota... (20251107) (#12853) 
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
Co-authored-by: Stefan He <hebiaobuaa@gmail.com>
 2025-11-07 22:07:51 -08:00
Yuan Luoandluoyuan.luo bb517fe393 [HotFix] Disable torch dynamo for mrope_triton kernel (#12593) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
 2025-11-04 23:26:56 +08:00
fzyzcjy 326c84c493 Compiling rope while preserving true on policy (#12161) 2025-10-28 08:02:17 +08:00
Chunyuan WU c11b34d599 rope xpu: fix missing argument 'fused_set_kv_buffer_arg' and replace native with sgl_kernel_xpu impl (#12006) 2025-10-28 01:02:18 +08:00
Yuan Luoandluoyuan.luo f389f01714 Optimize triton_mrope with torch compile (#12112) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
 2025-10-27 23:49:22 +08:00
Yuxuan Zhang a88b006ecf GLM-4-0414 and GLM-4.1V Code Refactor (#12117) 2025-10-27 16:57:07 +08:00
fzyzcjy 20bd2271e2 Support true on-policy (#12058) 2025-10-25 10:23:42 +08:00
b8zhong 8ae9d4bb41 Revert "[ROCm] Remove vLLM rope dependency & use AITER impl" (#12028) 2025-10-23 12:42:59 -07:00
b8zhong 4d4feccbb2 [ROCm] Remove vLLM rope dependency & use AITER impl (#11322) 2025-10-22 19:17:34 -07:00
Meng, HengyuguangyeyDiweiSun
 		b113c72e7a Init attention backend for Intel XPU (#10656) 
Co-authored-by: guangyey <guangye.yu@intel.com>
Co-authored-by: DiweiSun <105627594+DiweiSun@users.noreply.github.com>
 2025-10-21 11:41:28 +08:00
zhangdonghao-zdh fb6cc7b000 Fix RotaryEmbedding for fp32 input (#11843) 2025-10-21 10:56:48 +08:00
Yuan Luoluoyuan.luo羽癫b8zhong
 		74de76c685 Revise MRotaryEmbedding's forward (#11859) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
Co-authored-by: 羽癫 <yudian.zy@antgroup.com>
Co-authored-by: b8zhong <b8zhong@uwaterloo.ca>
 2025-10-21 10:38:29 +08:00
Yuan Luoluoyuan.luob8zhong
 		271d3d0d50 Support mrope triton kernel and add unit test (#11722) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
Co-authored-by: b8zhong <b8zhong@uwaterloo.ca>
 2025-10-20 11:51:07 +08:00
Liangsheng Yin 57e25de756 Revert "Fix: Dynamic RoPE Cache Expansion to Prevent Position-ID Out-of-Bounds in EAGLE + Long-Sequence Workloads" (#11827) 2025-10-19 19:44:06 +08:00
YAMY 80407b0493 Fix: Dynamic RoPE Cache Expansion to Prevent Position-ID Out-of-Bounds in EAGLE + Long-Sequence Workloads (#10788) 2025-10-19 11:37:43 +08:00
MickandXinyuan Tong 86b04d25b3 model: qwen3-omni (thinker-only) (#10911) 
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
 2025-10-16 13:20:38 -07:00
DiweiSunhuaiyuzhMa Mingfeicoderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com>
 		4c03dbaaef [CI][XPU]enable sglang CI on Intel XPU (#9493) 
Co-authored-by: huaiyuzh <huaiyu.zheng@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com>
 2025-10-15 17:13:19 -07:00
Mick f35f120d70 fix: fix video input for qwen3-vl (#11442) 2025-10-13 09:30:43 -07:00
Yuan Luoandluoyuan.luo 0b6f535f66 [Reland] perf: optimize qwen-vl with symm mem allreduce (#11457) 
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
 2025-10-13 17:51:25 +08:00
Lianmin Zheng b4408e6098 Revert "fix: fix video input for qwen3-vl" (#11437) 2025-10-10 12:44:40 -07:00
Cheng Wan 52fcbbb8bd Revert "perf: optimize qwen-vl with symm mem allreduce" (#11436) 2025-10-10 12:30:05 -07:00