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chenchenghao/sglang
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Code Issues Pull Requests Actions 13 Packages Projects Releases Wiki Activity
10,877 Commits 1 Branch 0 Tags
09acec19082672ec62340520a352bb7c444f9ac3
Commit Graph
9 Commits
Author SHA1 Message Date
shubham singhalandsys-lpot-val a0d085c16d Adding correct path for module not found error while collecting test (#19778)
Co-authored-by: sys-lpot-val <sys_lpot_val@intel.com>
2026-03-06 16:26:16 -08:00
Yuwei An c64274c746 Piecewise Cuda Graph set default (#16331) 2026-03-02 23:18:07 +08:00
Yuan Luoandluoyuan.luo 31c7dc9d99 [VLM] Introduce FlashInfer CUDNN Prefill as ViT Backend (#19003)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
2026-02-24 19:49:22 +08:00
Hudson Xing c1282da236 fix(ci): apply MMMU retry logic to all affected test files (#17329) 2026-01-19 10:00:29 -08:00
Baizhou Zhang f35b5da521 [CI] Append test variant name to markdown report header in nightly test (#16166) 2025-12-31 00:09:24 +08:00
Yuan Luoandluoyuan.luo 019517a356 [VLM] Support ViT Piecewise CUDA Graph for Qwen3-VL (#15320)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
2025-12-20 21:00:07 +08:00
Yuan Luoluoyuan.luokousakawang
3b8a824b8b [VLM] Support VLM ViT Piecewise CUDA Graph (#14422)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
Co-authored-by: kousakawang <wanghanpei@bytedance.com>
2025-12-13 20:49:40 +08:00
YAMY decb48965d [DeepSeekV3.2] Enable pure TP & Partial DP Attention (#13646) 2025-11-30 15:59:23 -08:00
alisonshao 6b262ac839 Test reorganization: Move tests to manual/ (#13610) 2025-11-20 13:41:58 -08:00
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