[AMD] Fix accuracy issue when running TP4 dsv3 model with mtp (#18607)

Co-authored-by: YC Tseng <yctseng@amd.com>
Co-authored-by: kkHuang-amd <wunhuang@amd.com>
This commit is contained in:
Thomas Wang
2026-02-12 17:13:16 +08:00
committed by GitHub
parent d6f0ef677b
commit e20e6c28b9
2 changed files with 9 additions and 5 deletions

View File

@@ -195,11 +195,15 @@ class AiterAttnBackend(AttentionBackend):
)
global _use_mla_ps_kernel, fast_mode, intra_batch_mode
if self.num_head == 32:
fast_mode = True
intra_batch_mode = False
# current persist a16w16 mla_decode kernel does not support head_num = 128
# need to fall back to non-persist
# only use mla_ps_kernel when fp8 kv_cache
# for non-fp8 kv_cache, use non-persist kernel to avoid performance degradation
if self.kv_cache_dtype is not fp8_dtype:
# for non-fp8 kv_cache on tp8, use non-persist kernel to avoid performance degradation
if self.num_head == 16 and self.kv_cache_dtype is not fp8_dtype:
_use_mla_ps_kernel = False
fast_mode = False
intra_batch_mode = False
@@ -301,7 +305,7 @@ class AiterAttnBackend(AttentionBackend):
kv_last_page_len,
self.num_head // nhead_kv,
nhead_kv,
True,
False,
work_metadata,
work_info_set,
work_indptr,