[AMD] Enable ROCm kvcache JIT path and add AMD CI coverage. (#18992)
Co-authored-by: Cursor <cursoragent@cursor.com>
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@@ -14,6 +14,9 @@ from sglang.jit_kernel.benchmark.utils import (
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)
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from sglang.jit_kernel.kvcache import store_cache
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_is_hip = bool(torch.version.hip)
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HAS_AOT_STORE_CACHE = hasattr(torch.ops.sgl_kernel, "store_kv_cache")
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def sglang_aot_store_cache(
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k: torch.Tensor,
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@@ -77,9 +80,14 @@ ITEM_SIZE = get_benchmark_range(
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ci_range=[1024],
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)
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LINE_VALS = ["aot", "jit", "torch_compile", "torch_streams"]
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LINE_NAMES = ["SGL AOT Kernel", "SGL JIT Kernel", "PyTorch Compile", "PyTorch 2 Stream"]
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STYLES = [("orange", "-"), ("blue", "--"), ("red", ":"), ("green", "-.")]
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LINE_VALS = ["jit", "torch_compile", "torch_streams"]
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LINE_NAMES = ["SGL JIT Kernel", "PyTorch Compile", "PyTorch 2 Stream"]
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STYLES = [("blue", "--"), ("red", ":"), ("green", "-.")]
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# Keep non-HIP benchmark lines unchanged; only HIP tolerates missing AOT op.
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if (not _is_hip) or HAS_AOT_STORE_CACHE:
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LINE_VALS = ["aot"] + LINE_VALS
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LINE_NAMES = ["SGL AOT Kernel"] + LINE_NAMES
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STYLES = [("orange", "-")] + STYLES
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X_NAMES = ["item_size", "batch_size"]
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CONFIGS = list(itertools.product(ITEM_SIZE, BS_RANGE))
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@@ -116,11 +124,12 @@ def benchmark(
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torch.cuda.synchronize()
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FN_MAP = {
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"aot": sglang_aot_store_cache,
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"jit": sglang_jit_store_cache,
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"torch_compile": torch_compile_store_cache,
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"torch_streams": torch_streams_store_cache,
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}
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if (not _is_hip) or HAS_AOT_STORE_CACHE:
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FN_MAP["aot"] = sglang_aot_store_cache
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def fn():
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impl = FN_MAP[provider]
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