[kernel slimming] Clean many useless sgl-kernel deprecated kernels (#20277)
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@@ -1,4 +1,4 @@
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from typing import Optional, Tuple
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from typing import Optional
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import torch
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from sgl_kernel.utils import _get_cache_buf
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@@ -140,17 +140,6 @@ sgl_per_token_group_quant_fp8 = sgl_per_token_group_quant_8bit
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sgl_per_token_group_quant_int8 = sgl_per_token_group_quant_8bit
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def sgl_per_tensor_quant_fp8(
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input: torch.Tensor,
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output_q: torch.Tensor,
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output_s: torch.Tensor,
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is_static: bool,
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) -> None:
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torch.ops.sgl_kernel.sgl_per_tensor_quant_fp8.default(
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input, output_q, output_s, is_static
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)
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def sgl_per_token_quant_fp8(
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input: torch.Tensor,
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output_q: torch.Tensor,
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@@ -159,54 +148,6 @@ def sgl_per_token_quant_fp8(
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torch.ops.sgl_kernel.sgl_per_token_quant_fp8.default(input, output_q, output_s)
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def cutlass_scaled_fp4_mm(
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a: torch.Tensor,
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b: torch.Tensor,
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block_scale_a: torch.Tensor,
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block_scale_b: torch.Tensor,
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alpha: torch.Tensor,
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out_dtype: torch.dtype,
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) -> torch.Tensor:
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from sglang.jit_kernel.nvfp4 import (
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cutlass_scaled_fp4_mm as jit_cutlass_scaled_fp4_mm,
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)
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return jit_cutlass_scaled_fp4_mm(
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a,
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b,
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block_scale_a,
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block_scale_b,
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alpha,
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out_dtype,
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)
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def scaled_fp4_quant(
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input: torch.Tensor, input_global_scale: torch.Tensor
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) -> Tuple[torch.Tensor, torch.Tensor]:
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"""
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Quantize input tensor to FP4 and return quantized tensor and scale.
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This function quantizes the last dimension of the given tensor `input`. For
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every 16 consecutive elements, a single dynamically computed scaling factor
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is shared. This scaling factor is quantized using the `input_global_scale`
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and is stored in a swizzled layout (see
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https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-scale-factor-b-layout-4x).
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Args:
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input: The input tensor to be quantized to FP4
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input_global_scale: A scalar scaling factor for the entire tensor.
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Returns:
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Tuple[torch.Tensor, torch.Tensor]: The output tensor in FP4 but every
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two values are packed into a uint8 and float8_e4m3 scaling factors
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in a sizzled layout.
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"""
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from sglang.jit_kernel.nvfp4 import scaled_fp4_quant as jit_scaled_fp4_quant
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return jit_scaled_fp4_quant(input, input_global_scale)
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def qserve_w4a8_per_chn_gemm(
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in_feats: torch.Tensor,
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kernel: torch.Tensor,
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@@ -280,73 +221,6 @@ def shuffle_rows(input_tensor, dst2src_map, output_tensor_shape):
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return output_tensor
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def scaled_fp4_grouped_quant(
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input_tensor: torch.Tensor,
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input_global_scale: torch.Tensor,
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mask: torch.Tensor,
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):
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"""
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Quantize input tensor to FP4 and return quantized tensor and scale, for
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grouped gemm inputs (e.g., grouped_gemm_nt_masked for flashinfer).
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Args:
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input: The input tensor to be quantized to FP4, with shape (l, m, k)
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l is number of groups, m is number of tokens per group, k is number of features.
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input_global_scale: A scalar scaling factor for the entire tensor, with
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shape (l,).
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Outputs:
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output: The quantized tensor in FP4, with shape (m, k // 2, l) but the physical
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layout is (l, m, k // 2). `// 2` is because two fp4 values are packed into
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an uint8.
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output_scales: The blockscale tensor in FP8-E4M3, with shape (32, 4, rm, 4, rk, l)
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but the physical layout is (l, rm, rk, 32, 4, 4).
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Note:
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For the shape of output_scales, `32 * 4 * rm` is a padded m to nearest multiple of 128.
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`4 * rk` is a padded `k // 16` to nearest multiple of 4. These layout constants are
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required by the NVIDIA Blackwell MMA operations.
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"""
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from sglang.jit_kernel.nvfp4 import (
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scaled_fp4_grouped_quant as jit_scaled_fp4_grouped_quant,
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)
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return jit_scaled_fp4_grouped_quant(input_tensor, input_global_scale, mask)
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def silu_and_mul_scaled_fp4_grouped_quant(
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input_tensor: torch.Tensor,
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input_global_scale: torch.Tensor,
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mask: torch.Tensor,
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):
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"""
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Quantize input tensor to FP4 and return quantized tensor and scale, for
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grouped gemm inputs (e.g., grouped_gemm_nt_masked for flashinfer).
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Args:
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input: The input tensor to be quantized to FP4, with shape (l, m, k * 2)
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l is number of groups, m is number of tokens per group, k is number of features.
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input_global_scale: A scalar scaling factor for the entire tensor, with
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shape (l,).
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mask: The mask tensor, with shape (l,)
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Outputs:
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output: The quantized tensor in FP4, with shape (m, k // 2, l) but the physical
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layout is (l, m, k // 2). `// 2` is because two fp4 values are packed into
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an uint8.
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output_scales: The blockscale tensor in FP8-E4M3, with shape (32, 4, rm, 4, rk, l)
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but the physical layout is (l, rm, rk, 32, 4, 4).
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Note:
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For the shape of output_scales, `32 * 4 * rm` is a padded m to nearest multiple of 128.
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`4 * rk` is a padded `k // 16` to nearest multiple of 4. These layout constants are
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required by the NVIDIA Blackwell MMA operations.
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"""
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from sglang.jit_kernel.nvfp4 import (
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silu_and_mul_scaled_fp4_grouped_quant as jit_silu_and_mul_scaled_fp4_grouped_quant,
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)
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return jit_silu_and_mul_scaled_fp4_grouped_quant(
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input_tensor,
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input_global_scale,
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mask,
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)
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# GPTQ kernels
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def gptq_gemm(
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a: torch.Tensor,
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