498 lines
28 KiB
Plaintext
498 lines
28 KiB
Plaintext
#pragma once
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wunknown-attributes"
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#include <cutlass/arch/barrier.h>
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#include <deep_gemm/common/scheduler.cuh>
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#include <deep_gemm/common/utils.cuh>
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#include <deep_gemm/common/sm100_utils.cuh>
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namespace deep_gemm {
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using namespace deep_gemm::sm100;
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template <cute::UMMA::Major kMajorA, cute::UMMA::Major kMajorB,
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uint32_t SHAPE_M, uint32_t SHAPE_N, uint32_t SHAPE_K,
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uint32_t BLOCK_M, uint32_t BLOCK_N, uint32_t BLOCK_K,
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uint32_t kNumGroups,
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uint32_t kSwizzleAMode, uint32_t kSwizzleBMode, uint32_t kSwizzleCDMode,
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uint32_t kNumStages, uint32_t kNumLastStages,
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uint32_t kNumNonEpilogueThreads, uint32_t kNumEpilogueThreads,
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uint32_t kNumMulticast, bool kIsMulticastOnA,
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uint32_t kNumSMs,
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GemmType kGemmType, bool kWithAccumulation, typename cd_dtype_t,
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uint64_t kTensorCoreUtilControl>
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__global__ void __launch_bounds__(kNumNonEpilogueThreads + kNumEpilogueThreads, 1)
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sm100_bf16_gemm_impl(int* grouped_layout,
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uint32_t shape_m, uint32_t shape_n, uint32_t shape_k,
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const __grid_constant__ cute::TmaDescriptor tensor_map_a,
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const __grid_constant__ cute::TmaDescriptor tensor_map_b,
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const __grid_constant__ cute::TmaDescriptor tensor_map_c,
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const __grid_constant__ cute::TmaDescriptor tensor_map_d) {
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#if (defined(__CUDA_ARCH__) and (__CUDA_ARCH__ >= 1000)) or defined(__CLION_IDE__)
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using Barrier = cutlass::arch::ClusterTransactionBarrier;
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using Allocator = cute::conditional_t<kNumMulticast == 1, cute::TMEM::Allocator1Sm, cute::TMEM::Allocator2Sm>;
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// GEMM with accumulation must have FP32 output
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if constexpr (kWithAccumulation)
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DG_STATIC_ASSERT(cute::is_same_v<cd_dtype_t, float>, "Invalid C/D data dtype");
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// Configs
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constexpr uint32_t LAYOUT_AD_M = 128;
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constexpr uint32_t kNumMWaves = BLOCK_M / LAYOUT_AD_M;
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constexpr uint32_t kNumTMAStoreStages = 2;
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DG_STATIC_ASSERT(BLOCK_K == 64, "Invalid block K");
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DG_STATIC_ASSERT(BLOCK_M % LAYOUT_AD_M == 0 and 2 % kNumMWaves == 0, "Invalid block M");
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// Overwrite shape constants if the compiler gives
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shape_m = SHAPE_M != 0 ? SHAPE_M : shape_m;
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shape_n = SHAPE_N != 0 ? SHAPE_N : shape_n;
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shape_k = SHAPE_K != 0 ? SHAPE_K : shape_k;
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// Utils
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bool is_leader_cta = cute::block_rank_in_cluster() == 0;
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const auto warp_idx = cutlass::canonical_warp_idx_sync();
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const auto lane_idx = get_lane_idx();
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// Align to 1024 bytes for swizzle-128B
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extern __shared__ __align__(1024) uint8_t smem_buffer[];
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// 2-CTA MMA
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constexpr uint32_t LOAD_BLOCK_M = BLOCK_M / (kIsMulticastOnA ? kNumMulticast: 1);
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constexpr uint32_t LOAD_BLOCK_N = BLOCK_N / (kIsMulticastOnA ? 1 : kNumMulticast);
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constexpr uint32_t STORE_BLOCK_M = cute::min<uint32_t>(BLOCK_M, LAYOUT_AD_M);
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constexpr uint32_t STORE_BLOCK_N = kSwizzleCDMode / sizeof(cd_dtype_t);
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DG_STATIC_ASSERT(not kIsMulticastOnA or kNumMulticast == 1, "Invalid multicast");
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DG_STATIC_ASSERT(LOAD_BLOCK_M == BLOCK_M and BLOCK_M % LAYOUT_AD_M == 0, "Only support tensor memory layout A/D");
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DG_STATIC_ASSERT(kNumMulticast == 1 or kNumMulticast == 2, "Only support 1/2 multicast");
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// Share memory sizes
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constexpr uint32_t SMEM_CD_SIZE_PER_STAGE = STORE_BLOCK_M * kSwizzleCDMode;
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constexpr uint32_t SMEM_CD_SIZE = SMEM_CD_SIZE_PER_STAGE * kNumTMAStoreStages;
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constexpr uint32_t SMEM_A_SIZE_PER_STAGE = LOAD_BLOCK_M * BLOCK_K * sizeof(cutlass::bfloat16_t);
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constexpr uint32_t SMEM_B_SIZE_PER_STAGE = LOAD_BLOCK_N * BLOCK_K * sizeof(cutlass::bfloat16_t);
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DG_STATIC_ASSERT(SMEM_CD_SIZE % 1024 == 0, "Shared memory of A/B must be aligned to 1024 bytes");
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DG_STATIC_ASSERT(kNumTMAStoreStages >= 1, "Invalid number of TMA stages");
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// Automatically deduce the number of epilogue stages (1 or 2), according to the tensor memory size
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// TODO: test cases of `kNumMWaves == 2 and kNumEpilogueStages == 2`
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constexpr uint32_t kNumEpilogueStages = (2 * kNumMWaves * BLOCK_N) > 512 ? 1 : 2;
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// Real tensor memory size and offsets
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constexpr uint32_t kNumAccumTmemCols = kNumEpilogueStages * kNumMWaves * BLOCK_N;
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constexpr uint32_t kNumTmemCols = get_num_aligned_tmem_cols<kNumAccumTmemCols>();
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// Prefetch TMA descriptors at the very beginning
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if (threadIdx.x == 0) {
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// NOTES: `reinterpret_cast` must be here, or NVRTC will fail
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cute::prefetch_tma_descriptor(&tensor_map_a);
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cute::prefetch_tma_descriptor(&tensor_map_b);
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cute::prefetch_tma_descriptor(&tensor_map_d);
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if constexpr (kWithAccumulation)
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cute::prefetch_tma_descriptor(&tensor_map_c);
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}
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// Data on shared memory (layout as ordered below)
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cd_dtype_t* smem_cd[kNumTMAStoreStages];
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cutlass::bfloat16_t* smem_a[kNumStages];
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cutlass::bfloat16_t* smem_b[kNumStages];
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// Fill D/A/B pointers
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#pragma unroll
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for (uint32_t i = 0; i < kNumTMAStoreStages; ++ i)
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smem_cd[i] = reinterpret_cast<cd_dtype_t*>(smem_buffer + i * SMEM_CD_SIZE_PER_STAGE);
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#pragma unroll
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for (uint32_t i = 0; i < kNumStages; ++ i) {
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smem_a[i] = reinterpret_cast<cutlass::bfloat16_t*>(smem_buffer + SMEM_CD_SIZE + i * SMEM_A_SIZE_PER_STAGE);
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smem_b[i] = reinterpret_cast<cutlass::bfloat16_t*>(smem_buffer + SMEM_CD_SIZE + kNumStages * SMEM_A_SIZE_PER_STAGE + i * SMEM_B_SIZE_PER_STAGE);
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}
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// Fill barriers
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auto barrier_start_ptr = reinterpret_cast<Barrier*>(smem_buffer + SMEM_CD_SIZE +
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kNumStages * (SMEM_A_SIZE_PER_STAGE + SMEM_B_SIZE_PER_STAGE));
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auto full_barriers = PatternVisitor([=](const uint32_t& i) { return barrier_start_ptr + (i); });
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auto empty_barriers = PatternVisitor([=](const uint32_t& i) { return barrier_start_ptr + (kNumStages + i); });
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auto tmem_full_barriers = PatternVisitor([=](const uint32_t& i) { return barrier_start_ptr + (kNumStages * 2 + i); });
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auto tmem_empty_barriers = PatternVisitor([=](const uint32_t& i) { return barrier_start_ptr + (kNumStages * 2 + kNumEpilogueStages + i); });
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// Fill the tensor memory pointer
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auto tmem_ptr_in_smem = reinterpret_cast<uint32_t*>(barrier_start_ptr + kNumStages * 3 + kNumEpilogueStages * 2);
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DG_STATIC_ASSERT(32 <= kNumTmemCols and kNumTmemCols <= 512, "Invalid tensor memory columns");
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// Initialize barriers
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if (threadIdx.x == 0) {
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#pragma unroll
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for (uint32_t i = 0; i < kNumStages; ++ i) {
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// Arrive only at the leader CTA
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full_barriers[i]->init(kNumMulticast);
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// Arrive at all CTAs
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empty_barriers[i]->init(1);
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}
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#pragma unroll
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for (uint32_t i = 0; i < kNumEpilogueStages; ++ i) {
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// Arrive at all CTAs
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tmem_full_barriers[i]->init(1);
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// Arrive only at the leader CTA
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tmem_empty_barriers[i]->init(kNumMulticast * kNumEpilogueThreads);
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}
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// Make initialized barrier visible in async proxy
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cutlass::arch::fence_view_async_shared();
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cutlass::arch::fence_barrier_init();
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} else if (threadIdx.x >= 32 and threadIdx.x < 64) {
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// Allocate tensor memory
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Allocator().allocate(kNumTmemCols, tmem_ptr_in_smem);
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}
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kNumMulticast > 1 ? cute::cluster_sync() : __syncthreads();
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// Block scheduler
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uint32_t m_block_idx, n_block_idx;
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auto scheduler = Scheduler<kGemmType, BLOCK_M, BLOCK_N, kNumGroups, kNumMulticast, kIsMulticastOnA, kNumSMs>(shape_m, shape_n, grouped_layout);
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// For pipeline unrolling
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struct DivisibleK {};
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struct NotDivisibleK {};
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uint32_t phase = 0;
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auto launch_k_iterations = [&](const auto& func) {
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const uint32_t current_shape_k = (kGemmType == GemmType::KGroupedContiguous ? scheduler.current_shape_k : shape_k);
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const uint32_t num_iterations = ceil_div(current_shape_k, kNumStages * BLOCK_K);
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const uint32_t num_last_stages = ceil_div(current_shape_k, BLOCK_K) % kNumStages;
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// TODO: refactor here
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if (num_last_stages == 0) {
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for (uint32_t k_iter = 0; k_iter < num_iterations; ++ k_iter, phase ^= 1)
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func(k_iter, DivisibleK{}, k_iter == num_iterations - 1, num_last_stages);
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} else {
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for (uint32_t k_iter = 0; k_iter < num_iterations - 1; ++ k_iter, phase ^= 1)
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func(k_iter, DivisibleK{}, false, num_last_stages);
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func(num_iterations - 1, NotDivisibleK{}, true, num_last_stages), phase ^= 1;
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}
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};
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auto dispatch_accum_stage_idx = [&](uint32_t accum_stage_idx, const auto& func) {
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DG_STATIC_ASSERT(1 <= kNumEpilogueStages and kNumEpilogueStages <= 2,
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"Too many epilogue stages, please modify the Python heuristic as well");
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accum_stage_idx == 0 ? func(0) : func(1);
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};
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// Dispatch warps into different roles
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if (warp_idx == 0) {
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// TMA load warp
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// Persistently schedule over blocks
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while (scheduler.get_next_block(m_block_idx, n_block_idx)) {
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launch_k_iterations([&](uint32_t k_iter, auto type, bool is_last_iter, uint32_t num_last_stages) {
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constexpr bool kHasDivisibleStages = cute::is_same_v<decltype(type), DivisibleK>;
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const uint32_t kNumInnerStages = kHasDivisibleStages ? kNumStages : num_last_stages;
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#pragma unroll
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for (uint32_t s = 0; s < kNumInnerStages; ++ s) {
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// Wait consumer release
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empty_barriers[s]->wait(phase ^ 1);
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// Compute offsets
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// NOTES: the group is always concatenated with the outer dimension
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uint32_t m_idx = scheduler.template get_global_idx<(kGemmType == GemmType::MGroupedMasked), KGroupedIndexType::MN> (
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shape_m, BLOCK_M, m_block_idx);
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uint32_t n_idx = scheduler.template get_global_idx<(kMajorB == cute::UMMA::Major::K), KGroupedIndexType::MN> (
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shape_n, BLOCK_N, n_block_idx, m_block_idx);
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// NOTES: `k_idx` is actually the k index default for K-major, while `k_b_idx` may be MN-major
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// And for all m-grouped GEMMs, A must be K-majored
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DG_STATIC_ASSERT(kGemmType == GemmType::Normal or kGemmType == GemmType::KGroupedContiguous or kMajorA == cute::UMMA::Major::K, "Invalid major");
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uint32_t k_block_idx = k_iter * kNumStages + s;
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uint32_t k_idx = k_block_idx * BLOCK_K;
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uint32_t k_a_idx = scheduler.template get_global_idx<(kMajorA == cute::UMMA::Major::MN), KGroupedIndexType::K> (
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shape_k, BLOCK_K, k_block_idx, m_block_idx);
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uint32_t k_b_idx = scheduler.template get_global_idx<(kMajorB == cute::UMMA::Major::MN), KGroupedIndexType::K> (
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shape_k, BLOCK_K, k_block_idx, m_block_idx);
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// Add 2 CTA offsets
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if constexpr (kNumMulticast > 1) {
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m_idx += kIsMulticastOnA ? (cute::block_rank_in_cluster() * LOAD_BLOCK_M) : 0;
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n_idx += kIsMulticastOnA ? 0 : (cute::block_rank_in_cluster() * LOAD_BLOCK_N);
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}
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// Issue TMAs
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if (cute::elect_one_sync()) {
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if constexpr (kMajorA == cute::UMMA::Major::K)
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tma_copy<BLOCK_K, LOAD_BLOCK_M, kSwizzleAMode, kNumMulticast>(&tensor_map_a, full_barriers[s], smem_a[s], k_a_idx, m_idx);
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if constexpr (kMajorA == cute::UMMA::Major::MN)
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tma_copy<LOAD_BLOCK_M, BLOCK_K, kSwizzleAMode, kNumMulticast>(&tensor_map_a, full_barriers[s], smem_a[s], m_idx, k_a_idx);
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if constexpr (kMajorB == cute::UMMA::Major::K)
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tma_copy<BLOCK_K, LOAD_BLOCK_N, kSwizzleBMode, kNumMulticast>(&tensor_map_b, full_barriers[s], smem_b[s], k_b_idx, n_idx);
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if constexpr (kMajorB == cute::UMMA::Major::MN)
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tma_copy<LOAD_BLOCK_N, BLOCK_K, kSwizzleBMode, kNumMulticast>(&tensor_map_b, full_barriers[s], smem_b[s], n_idx, k_b_idx);
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}
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// Arrive at full barriers
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constexpr uint32_t kNumArrivalBytes = SMEM_A_SIZE_PER_STAGE + SMEM_B_SIZE_PER_STAGE;
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if (is_leader_cta and cute::elect_one_sync())
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full_barriers[s]->arrive_and_expect_tx(kNumArrivalBytes * kNumMulticast);
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if (not is_leader_cta and cute::elect_one_sync())
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full_barriers[s]->arrive(0u);
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}
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// Wait unaligned cases
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#pragma unroll
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for (uint32_t s = kNumInnerStages; s < kNumStages; ++ s) {
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empty_barriers[s]->wait(phase ^ 1);
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if (is_leader_cta and cute::elect_one_sync())
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full_barriers[s]->arrive();
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if (not is_leader_cta and cute::elect_one_sync())
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full_barriers[s]->arrive(0u);
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}
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});
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}
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} else if (warp_idx == 1 and is_leader_cta) {
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// MMA issue warp
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// NOTES: only the leader CTA will do this
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// Make instruction descriptor
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// TODO: refactor `UMMA_M` calculation
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constexpr uint32_t UMMA_M = LAYOUT_AD_M * (kIsMulticastOnA ? 1 : kNumMulticast);
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constexpr uint32_t UMMA_N = BLOCK_N * (kIsMulticastOnA ? kNumMulticast : 1);
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constexpr uint32_t UMMA_K = 32 / sizeof(cutlass::bfloat16_t);
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auto instr_desc = cute::UMMA::make_instr_desc<cutlass::bfloat16_t, cutlass::bfloat16_t, float, UMMA_M, UMMA_N, kMajorA, kMajorB>();
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DG_STATIC_ASSERT(kNumStages <= 32, "Too many stages");
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auto a_desc = make_umma_desc<kMajorA, BLOCK_M, BLOCK_K, kSwizzleAMode>(smem_a[0], 0, 0);
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auto b_desc = make_umma_desc<kMajorB, BLOCK_N, BLOCK_K, kSwizzleBMode>(smem_b[0], 0, 0);
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uint32_t a_desc_lo = lane_idx < kNumStages ? a_desc.lo + lane_idx * SMEM_A_SIZE_PER_STAGE / 16 : 0u;
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uint32_t b_desc_lo = lane_idx < kNumStages ? b_desc.lo + lane_idx * SMEM_B_SIZE_PER_STAGE / 16 : 0u;
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// Checks for MMA instructions
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// NOTES: CUTLASS does not have such checks except the MMA traits, but we are not using these traits
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DG_STATIC_ASSERT((UMMA_M == 64 and UMMA_N % 8 == 0 and 8 <= UMMA_N and UMMA_N <= 256) or
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(UMMA_M == 128 and UMMA_N % 16 == 0 and 16 <= UMMA_N and UMMA_N <= 256) or
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(UMMA_M == 256 and UMMA_N % 16 == 0 and 16 <= UMMA_N and UMMA_N <= 256),
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"Invalid MMA instruction shape");
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// Persistently schedule over blocks
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while (scheduler.get_next_block(m_block_idx, n_block_idx)) {
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dispatch_accum_stage_idx(scheduler.current_iter % kNumEpilogueStages, [&](uint32_t accum_stage_idx) {
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// Wait tensor memory empty barrier arrival
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auto accum_phase_idx = (scheduler.current_iter / kNumEpilogueStages) & 1;
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tmem_empty_barriers[accum_stage_idx]->wait(accum_phase_idx ^ 1);
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tcgen05_after_thread_sync();
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// Empty barrier arrival
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auto empty_barrier_arrive = [&](uint32_t s, bool do_tmem_full_arrive) {
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auto umma_arrive = [](const uint64_t* barrier) {
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if constexpr (kNumMulticast == 1) {
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cutlass::arch::umma_arrive(barrier);
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} else {
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constexpr uint16_t kCTAMask = (1 << kNumMulticast) - 1;
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cutlass::arch::umma_arrive_multicast_2x1SM(barrier, kCTAMask);
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}
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};
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umma_arrive(reinterpret_cast<uint64_t*>(empty_barriers[s]));
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// NOTES: the tensor memory accumulator pipeline has nothing to do with multicasting
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if (do_tmem_full_arrive)
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umma_arrive(reinterpret_cast<uint64_t*>(tmem_full_barriers[accum_stage_idx]));
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};
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// Launch MMAs
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launch_k_iterations([&](uint32_t k_iter, auto type, bool is_last_iter, uint32_t num_last_stages) {
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constexpr bool kHasDivisibleStages = cute::is_same_v<decltype(type), DivisibleK>;
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const uint32_t kNumInnerStages = kHasDivisibleStages ? kNumStages : num_last_stages;
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#pragma unroll
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for (uint32_t s = 0; s < kNumInnerStages; ++ s) {
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// Wait TMA arrival
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full_barriers[s]->wait(phase);
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tcgen05_after_thread_sync();
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// Let tensor cores relax for lower possibility of frequency drop
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DG_STATIC_ASSERT(kTensorCoreUtilControl > 0, "Invalid tensor utilization control");
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if constexpr (kTensorCoreUtilControl < 100) {
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constexpr static uint64_t kNumUMMACycles = (2ull * BLOCK_M * BLOCK_N * BLOCK_K) / 8192ull;
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constexpr static uint64_t kNumDummyCycles = (100ull - kTensorCoreUtilControl) * kNumUMMACycles / kTensorCoreUtilControl;
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const auto& start_clock = clock64();
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if (cute::elect_one_sync())
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while (clock64() - start_clock < kNumDummyCycles) {}
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__syncwarp();
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}
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// Issue UMMA in the leader CTA
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using cute_mma_t = cute::conditional_t<kNumMulticast == 1,
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cute::SM100_MMA_F16BF16_SS <cutlass::bfloat16_t, cutlass::bfloat16_t, float, UMMA_M, UMMA_N, kMajorA, kMajorB>,
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cute::SM100_MMA_F16BF16_2x1SM_SS<cutlass::bfloat16_t, cutlass::bfloat16_t, float, UMMA_M, UMMA_N, kMajorA, kMajorB>>;
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const auto& runtime_instr_desc = cute::UMMA::make_runtime_instr_desc(instr_desc);
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const auto& a_desc_base_lo = __shfl_sync(0xffffffff, a_desc_lo, s);
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const auto& b_desc_base_lo = __shfl_sync(0xffffffff, b_desc_lo, s);
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#pragma unroll
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for (uint32_t k = 0; k < BLOCK_K / UMMA_K; ++ k) {
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b_desc.lo = advance_umma_desc_lo<kMajorB, BLOCK_N, kSwizzleBMode, cutlass::bfloat16_t>(b_desc_base_lo, 0, k * UMMA_K);
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#pragma unroll
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for (uint32_t w = 0; w < kNumMWaves; ++ w) {
|
|
a_desc.lo = advance_umma_desc_lo<kMajorA, BLOCK_M, kSwizzleAMode, cutlass::bfloat16_t>(a_desc_base_lo, w * LAYOUT_AD_M * BLOCK_K, k * UMMA_K);
|
|
cute_mma_t::fma(a_desc, b_desc,
|
|
accum_stage_idx * kNumMWaves * BLOCK_N + w * BLOCK_N,
|
|
k_iter > 0 or s > 0 or k > 0,
|
|
runtime_instr_desc);
|
|
}
|
|
}
|
|
|
|
// Commit to the mbarrier object
|
|
// No explicit `tcgen05.fence::before_thread_sync` is needed, as this is implicitly performed by `tcgen05.commit`
|
|
empty_barrier_arrive(s, is_last_iter and s == kNumInnerStages - 1);
|
|
}
|
|
|
|
// Wait unaligned cases
|
|
#pragma unroll
|
|
for (uint32_t s = kNumInnerStages; s < kNumStages; ++ s) {
|
|
full_barriers[s]->wait(phase);
|
|
empty_barrier_arrive(s, false);
|
|
}
|
|
});
|
|
});
|
|
}
|
|
} else if (warp_idx >= kNumNonEpilogueThreads / 32) {
|
|
// Epilogue warp groups
|
|
const auto epilogue_thread_idx = threadIdx.x - kNumNonEpilogueThreads;
|
|
const auto epilogue_warp_idx = warp_idx - (kNumNonEpilogueThreads / 32);
|
|
|
|
// NOTES: tensor memory addresses are simplified, as the hardware will ignore the warp index bits,
|
|
// i.e., no need for `tmem_ptr |= (epilogue_warp_idx * 32) << 16`.
|
|
// NOTES: we also forbid two CTAs to share the same SM and its tensor memory
|
|
DG_TRAP_ONLY_DEVICE_ASSERT(ld_shared(tmem_ptr_in_smem) == 0);
|
|
|
|
// TMA checks
|
|
constexpr uint32_t kNumBankGroupBytes = 16;
|
|
constexpr uint32_t kNumElemsPerBankGroup = kNumBankGroupBytes / sizeof(cd_dtype_t);
|
|
DG_STATIC_ASSERT(kSwizzleCDMode > 0, "TMA D must be swizzled");
|
|
DG_STATIC_ASSERT(STORE_BLOCK_N % kNumElemsPerBankGroup == 0, "Invalid swizzling");
|
|
|
|
// Persistently schedule over blocks
|
|
while (scheduler.get_next_block(m_block_idx, n_block_idx)) {
|
|
dispatch_accum_stage_idx(scheduler.current_iter % kNumEpilogueStages, [&](uint32_t accum_stage_idx) {
|
|
auto accum_phase_idx = (scheduler.current_iter / kNumEpilogueStages) & 1;
|
|
|
|
// Flush TMA stores
|
|
// NOTES: for the first store, we have to flush all previous TMA,
|
|
// as we don't share pipeline stages between two blocks
|
|
if (epilogue_thread_idx == 0)
|
|
cute::tma_store_wait<0>();
|
|
cutlass::arch::NamedBarrier(kNumEpilogueThreads).sync();
|
|
|
|
// Wait UMMA arrival
|
|
tmem_full_barriers[accum_stage_idx]->wait(accum_phase_idx);
|
|
tcgen05_after_thread_sync();
|
|
|
|
// Load from tensor memory into registers, and write shared memory with STSM
|
|
DG_STATIC_ASSERT(kNumEpilogueThreads == 128, "Epilogue threads not enough");
|
|
DG_STATIC_ASSERT(BLOCK_N % STORE_BLOCK_N == 0, "Invalid block sizes");
|
|
|
|
// Iterate over M waves
|
|
#pragma unroll
|
|
for (uint32_t w = 0; w < kNumMWaves; ++ w) {
|
|
// Issue every swizzled atom and pipeline STSM and TMA store
|
|
constexpr uint32_t kNumStores = BLOCK_N / STORE_BLOCK_N;
|
|
#pragma unroll
|
|
for (uint32_t s = 0; s < kNumStores; ++ s) {
|
|
// Wait shared memory to be released
|
|
const uint32_t iter_idx = w * kNumStores + s;
|
|
if (iter_idx >= kNumTMAStoreStages) {
|
|
if (epilogue_thread_idx == 0)
|
|
cute::tma_store_wait<kNumTMAStoreStages - 1>();
|
|
cutlass::arch::NamedBarrier(kNumEpilogueThreads).sync();
|
|
}
|
|
|
|
// The pipeline stage
|
|
const auto tma_stage_idx = iter_idx % kNumTMAStoreStages;
|
|
const auto m_idx = scheduler.template get_global_idx<(kGemmType != GemmType::MGroupedContiguous), KGroupedIndexType::MN>(shape_m, BLOCK_M, m_block_idx) + w * LAYOUT_AD_M;
|
|
const auto n_idx = n_block_idx * BLOCK_N + s * STORE_BLOCK_N;
|
|
|
|
// Store into shared memory
|
|
#pragma unroll
|
|
for (uint32_t i = 0; i < STORE_BLOCK_N / kNumElemsPerBankGroup; ++ i) {
|
|
// Calculate the index of the bank group to be written in the atom
|
|
auto bank_group_index = i + lane_idx * (kSwizzleCDMode / kNumBankGroupBytes);
|
|
|
|
// Reshape the atom in another view and swizzle
|
|
// - original: `(LAYOUT_AD_M, kSwizzleCDMode / kNumBankGroupBytes)`
|
|
// - new: `(LAYOUT_AD_M * kSwizzleCDMode / kNumBankGroupBytes / 8, 8)`
|
|
// NOTES: "8" is the number of bank groups, "16" is the swizzling pattern
|
|
constexpr bool kHasShortcut = (kSwizzleCDMode / kNumBankGroupBytes) == 8;
|
|
auto row = kHasShortcut ? (i / 8 + lane_idx) : (bank_group_index / 8);
|
|
auto col = kHasShortcut ? (i) : (bank_group_index % 8);
|
|
col ^= row % (kSwizzleCDMode / 16);
|
|
|
|
// Source and destination memory address
|
|
uint32_t tmem_addr = accum_stage_idx * kNumMWaves * BLOCK_N + // Accumulator offset
|
|
w * BLOCK_N + // Wave offset
|
|
s * STORE_BLOCK_N + i * kNumElemsPerBankGroup; // In-block offset
|
|
auto smem_ptr = reinterpret_cast<uint8_t*>(smem_cd[tma_stage_idx]) + // Base pointer
|
|
epilogue_warp_idx * 32 * kSwizzleCDMode + // Warp offset
|
|
row * (kNumBankGroupBytes * 8) + col * kNumBankGroupBytes; // In-atom offset
|
|
|
|
// Load from tensor memory, store into shared memory
|
|
uint32_t values[kNumElemsPerBankGroup];
|
|
if constexpr (cute::is_same_v<cd_dtype_t, float>) {
|
|
// For FP32 output, read and store
|
|
DG_STATIC_ASSERT(kNumElemsPerBankGroup == 4, "Invalid type");
|
|
cute::SM100_TMEM_LOAD_32dp32b4x::copy(tmem_addr,
|
|
values[0], values[1], values[2], values[3]);
|
|
cutlass::arch::fence_view_async_tmem_load();
|
|
st_shared(smem_ptr, values[0], values[1], values[2], values[3]);
|
|
} else {
|
|
// For BF16 output, read, cast and store
|
|
DG_STATIC_ASSERT(kNumElemsPerBankGroup == 8 and cute::is_same_v<cd_dtype_t, cutlass::bfloat16_t>, "Invalid type");
|
|
cute::SM100_TMEM_LOAD_32dp32b8x::copy(tmem_addr,
|
|
values[0], values[1], values[2], values[3],
|
|
values[4], values[5], values[6], values[7]);
|
|
cutlass::arch::fence_view_async_tmem_load();
|
|
st_shared(smem_ptr,
|
|
cast_into_bf16_and_pack(values[0], values[1]),
|
|
cast_into_bf16_and_pack(values[2], values[3]),
|
|
cast_into_bf16_and_pack(values[4], values[5]),
|
|
cast_into_bf16_and_pack(values[6], values[7]));
|
|
}
|
|
}
|
|
|
|
// Notify tensor memory empty (only at the leader CTA) arrival ASAP
|
|
// NOTES: only the last stage needs to do this
|
|
if (w == kNumMWaves - 1 and s == BLOCK_N / STORE_BLOCK_N - 1) {
|
|
tcgen05_before_thread_sync();
|
|
tmem_empty_barriers[accum_stage_idx]->arrive(0u);
|
|
}
|
|
__syncwarp();
|
|
|
|
// Synchronize all threads and issue TMA
|
|
cute::tma_store_fence();
|
|
cutlass::arch::NamedBarrier(kNumEpilogueThreads).sync();
|
|
if (epilogue_thread_idx == 0) {
|
|
using cute_tma_t = cute::conditional_t<kWithAccumulation,
|
|
cute::SM90_TMA_REDUCE_ADD_2D, cute::SM90_TMA_STORE_2D>;
|
|
cute_tma_t::copy(&tensor_map_d, smem_cd[tma_stage_idx], n_idx, m_idx);
|
|
cute::tma_store_arrive();
|
|
}
|
|
}
|
|
}
|
|
});
|
|
}
|
|
|
|
// Flush all stages in the pipeline to make TMA stores visible to the next kernel
|
|
if (epilogue_thread_idx == 0)
|
|
cute::tma_store_wait<0>();
|
|
|
|
// Deallocate tensor memory by warp 1
|
|
// NOTES: warp 0 is waiting TMA store
|
|
if (epilogue_warp_idx == 1)
|
|
Allocator().free(0, kNumTmemCols);
|
|
}
|
|
|
|
// To safely deconstruct all barriers, we need a cluster sync
|
|
// TODO: optimize it by another round of barrier waits
|
|
if constexpr (kNumMulticast > 1)
|
|
cute::cluster_sync();
|
|
#else
|
|
if (blockIdx.x == 0 and threadIdx.x == 0)
|
|
DG_DEVICE_ASSERT(false and "This kernel only support sm_100a/sm_101a");
|
|
#endif
|
|
}
|
|
|
|
}; // namespace deep_gemm
|
|
|
|
#pragma clang diagnostic pop
|