Add sm_100f support and make nvcc 13 happy (#157)
Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
This commit is contained in:
@@ -155,7 +155,7 @@ public:
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signature = fmt::format("NVCC{}.{}", nvcc_major, nvcc_minor);
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signature = fmt::format("NVCC{}.{}", nvcc_major, nvcc_minor);
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// The override the compiler flags
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// The override the compiler flags
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flags = fmt::format("{} -I{} --gpu-architecture=sm_{}a "
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flags = fmt::format("{} -I{} --gpu-architecture=sm_{} "
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"--compiler-options=-fPIC,-O3,-fconcepts,-Wno-deprecated-declarations,-Wno-abi "
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"--compiler-options=-fPIC,-O3,-fconcepts,-Wno-deprecated-declarations,-Wno-abi "
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"-cubin -O3 --expt-relaxed-constexpr --expt-extended-lambda",
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"-cubin -O3 --expt-relaxed-constexpr --expt-extended-lambda",
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flags, library_include_path.c_str(), device_runtime->get_arch());
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flags, library_include_path.c_str(), device_runtime->get_arch());
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@@ -205,7 +205,7 @@ public:
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}
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}
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// Override the compiler flags
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// Override the compiler flags
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flags = fmt::format("{} {}--gpu-architecture=sm_{}a -default-device {}",
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flags = fmt::format("{} {}--gpu-architecture=sm_{} -default-device {}",
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flags, include_dirs, device_runtime->get_arch(), pch_flags);
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flags, include_dirs, device_runtime->get_arch(), pch_flags);
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}
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}
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@@ -25,9 +25,12 @@ public:
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return {prop->major, prop->minor};
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return {prop->major, prop->minor};
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}
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}
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int get_arch() {
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std::string get_arch() {
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const auto& [major, minor] = get_arch_pair();
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const auto& [major, minor] = get_arch_pair();
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return major * 10 + minor;
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if (major == 10 && minor != 1) {
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return "100f";
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}
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return std::to_string(major * 10 + minor) + "a";
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}
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}
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int get_arch_major() {
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int get_arch_major() {
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@@ -33,6 +33,7 @@ sm100_fp8_gemm_1d1d_impl(int* grouped_layout,
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const __grid_constant__ cute::TmaDescriptor tensor_map_d) {
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const __grid_constant__ cute::TmaDescriptor tensor_map_d) {
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#if (defined(__CUDA_ARCH__) and (__CUDA_ARCH__ >= 1000)) or defined(__CLION_IDE__)
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#if (defined(__CUDA_ARCH__) and (__CUDA_ARCH__ >= 1000)) or defined(__CLION_IDE__)
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using Barrier = cutlass::arch::ClusterTransactionBarrier;
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using Barrier = cutlass::arch::ClusterTransactionBarrier;
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using Allocator = std::conditional_t<kNumMulticast == 1, cute::TMEM::Allocator1Sm, cute::TMEM::Allocator2Sm>;
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// GEMM with accumulation must have FP32 output
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// GEMM with accumulation must have FP32 output
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if constexpr (kWithAccumulation)
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if constexpr (kWithAccumulation)
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@@ -169,7 +170,7 @@ sm100_fp8_gemm_1d1d_impl(int* grouped_layout,
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cutlass::arch::fence_barrier_init();
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cutlass::arch::fence_barrier_init();
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} else if (threadIdx.x >= 32 and threadIdx.x < 64) {
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} else if (threadIdx.x >= 32 and threadIdx.x < 64) {
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// Allocate tensor memory
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// Allocate tensor memory
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cute::TMEM::Allocator1Sm().allocate(kNumTmemCols, tmem_ptr_in_smem);
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Allocator().allocate(kNumTmemCols, tmem_ptr_in_smem);
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}
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}
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kNumMulticast > 1 ? cute::cluster_sync() : __syncthreads();
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kNumMulticast > 1 ? cute::cluster_sync() : __syncthreads();
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@@ -585,7 +586,7 @@ sm100_fp8_gemm_1d1d_impl(int* grouped_layout,
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// NOTES: warp 0 is waiting TMA store
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// NOTES: warp 0 is waiting TMA store
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// TODO: do we need 2 SM allocation?
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// TODO: do we need 2 SM allocation?
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if (epilogue_warp_idx == 1)
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if (epilogue_warp_idx == 1)
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cute::TMEM::Allocator1Sm().free(0, kNumTmemCols);
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Allocator().free(0, kNumTmemCols);
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}
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}
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// To safely deconstruct all barriers, we need a cluster sync
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// To safely deconstruct all barriers, we need a cluster sync
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@@ -32,6 +32,7 @@ sm100_fp8_gemm_1d2d_impl(float* sfb, int* grouped_layout,
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const __grid_constant__ cute::TmaDescriptor tensor_map_sfa) {
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const __grid_constant__ cute::TmaDescriptor tensor_map_sfa) {
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#if (defined(__CUDA_ARCH__) and (__CUDA_ARCH__ >= 1000)) or defined(__CLION_IDE__)
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#if (defined(__CUDA_ARCH__) and (__CUDA_ARCH__ >= 1000)) or defined(__CLION_IDE__)
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using Barrier = cutlass::arch::ClusterTransactionBarrier;
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using Barrier = cutlass::arch::ClusterTransactionBarrier;
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using Allocator = std::conditional_t<kNumMulticast == 1, cute::TMEM::Allocator1Sm, cute::TMEM::Allocator2Sm>;
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// Scaling checks
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// Scaling checks
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DG_STATIC_ASSERT(BLOCK_K == 128, "Only support per-128-channel FP8 scaling");
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DG_STATIC_ASSERT(BLOCK_K == 128, "Only support per-128-channel FP8 scaling");
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@@ -152,7 +153,7 @@ sm100_fp8_gemm_1d2d_impl(float* sfb, int* grouped_layout,
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cutlass::arch::fence_barrier_init();
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cutlass::arch::fence_barrier_init();
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} else if (threadIdx.x >= 32 and threadIdx.x < 64) {
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} else if (threadIdx.x >= 32 and threadIdx.x < 64) {
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// Allocate tensor memory
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// Allocate tensor memory
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cute::TMEM::Allocator1Sm().allocate(kNumTmemCols, tmem_ptr_in_smem);
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Allocator().allocate(kNumTmemCols, tmem_ptr_in_smem);
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}
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}
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kNumMulticast > 1 ? cute::cluster_sync() : __syncthreads();
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kNumMulticast > 1 ? cute::cluster_sync() : __syncthreads();
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@@ -520,7 +521,7 @@ sm100_fp8_gemm_1d2d_impl(float* sfb, int* grouped_layout,
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// NOTES: warp 0 is waiting TMA store
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// NOTES: warp 0 is waiting TMA store
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// TODO: do we need 2 SM allocation?
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// TODO: do we need 2 SM allocation?
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if (epilogue_warp_idx == 1)
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if (epilogue_warp_idx == 1)
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cute::TMEM::Allocator1Sm().free(0, kNumTmemCols);
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Allocator().free(0, kNumTmemCols);
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}
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}
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// To safely deconstruct all barriers, we need a cluster sync
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// To safely deconstruct all barriers, we need a cluster sync
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